• 한국전기전자재료학회논문지
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• 제30권10호
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• pp.665-671
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• 2017

Herein, we report the fabrication of low-voltage N-type organic field-effect transistors by using high capacitance fluorinated polymer gate dielectrics such as P(VDF-TrFE), P(VDF-TrFE-CTFE), and P(VDF-TrFE-CFE). Electron-withdrawing functional groups in PVDF-based polymers typically cause the depletion of negative charge carriers and a high contact resistance in N-channel organic semiconductors. Therefore, we incorporated intermediate layers of a low-k polymerto prevent the formation of a direct interface between PVDF-based gate insulators and the semiconducting active layer. Consequently, electron depletion is inhibited, and the high charge resistance between the semiconductor and source/drain electrodes is remarkably improved by the in corporation of solution-processed charge injection layers.

• Nuclear Engineering and Technology
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• 제48권4호
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• pp.1047-1057
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• 2016

Design engineering process for field programmable gate array (FPGA)-based reactor trip functions are developed in this work. The process discussed in this work is based on the systems engineering approach. The overall design process is effectively implemented by combining with design and implementation processes. It transforms its overall development process from traditional V-model to Y-model. This approach gives the benefit of concurrent engineering of design work with software implementation. As a result, it reduces development time and effort. The design engineering process consisted of five activities, which are performed and discussed: needs/systems analysis; requirement analysis; functional analysis; design synthesis; and design verification and validation. Those activities are used to develop FPGA-based reactor bistable trip functions that trigger reactor trip when the process input value exceeds the setpoint. To implement design synthesis effectively, a model-based design technique is implied. The finite-state machine with data path structural modeling technique together with very high speed integrated circuit hardware description language and the Aldec Active-HDL tool are used to design, model, and verify the reactor bistable trip functions for nuclear power plants.

• 한국재료학회지
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• 제18권12호
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• pp.673-677
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• 2008

Calcia (CaO) stabilized cubic-$HfO_2$ is studied by density functional theory (DFT) with generalized gradient approximation (GGA). When a Ca atom is substituted for a Hf atom, an oxygen vacancy is produced to satisfy the charge neutrality. The lattice parameter of a $2{\times}2{\times}2$ cubic $HfO_2$ supercell then increases by $0.02\;{\AA}$. The oxygen atoms closest to the oxygen vacancy are attracted to the vacancy as the vacancy is positive compared to the oxygen ion. When the oxygen vacancy is located at the site closest to the Ca atom, the total energy of $HfO_2$ reaches its minimum. The energy barriers for the migration of the oxygen vacancy were calculated. The energy barriers between the first and the second nearest sites, the second and the third nearest sites, and the third and fourth nearest sites are 0.2, 0.5, and 0.24 eV, respectively. The oxygen vacancies at the third and fourth nearest sites relative to the Ca atom represent the oxygen vacancies in undoped $HfO_2$. Therefore, the energy barrier for oxygen migration in the $HfO_2$ gate dielectric is 0.24 eV, which can explain the origin of gate dielectric leakage.

• 한국정보처리학회논문지
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• 제3권5호
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• pp.1240-1252
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• 1996

본 논문에서는 게이트 어레이 레이아웃 형태에서 디지털 회로를 보다 발전적 인 방식으로 설계하도록 하는 기능 모듈 구현 전용 편집기를 제안한다. 구현된 편집기 에서의 기능 모듈 설계 작업은 전반적으로 설계자와의 대화 형식으로 이루어진다. 따라서, 설계자는 빠른 시간 내에 모듈을 설계할 수 있고 보다 만족스런 레이아웃 결과를 얻을 수 있다. 특히, 본 편집기에서는 IC원판을 구성하는 기초셀 형태에 대해 독립적이며, 배치및 배선 작업 시에 수동과 반자동 방식을 함께 사용할 수 있다는 특징이 있다. 또한 기존의 툴에서는 제공되지 않는 다양한 기능들이 추가되어있어 더욱 효율적으로 모듈 생성을 할 수 있다. 본 편집기는 X- 윈도우 Motif 환경하에서 C언어로 구현되었으며, 그 기능을 기존의 레이아웃 시스템인 Seadali를 사용했을 때와 비교하여 성능을 평가하였다. 구현한 편집기를 이용하면 설계 시간을 두 배정도 단축시킬 수 있다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.293-294
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• 2008

CaO stabilized cubic-$HfO_2$ is studied by using Density Functional Theory with GGA. When a Ca atom is substituted for a Hf atom, an oxygen vacancy is produced to satisfy the charge neutrality condition. When the oxygen vacancy is located at the first nearest site from the Ca atom, the total energy of $HfO_2$ is the most favorable. We calculate the energy barriers for the oxygen vacancy migration. The energy barriers between the first and the second nearest sites, the second and the third nearest sites, and the third and fourth nearest sites are 0.2, 0.5, 0.24 eV, respectively. The oxygen vacancies at the third and fourth nearest sites from the Ca atom represent the oxygen vacancies in undoped $HfO_2$. Therefore, the energy barrier for oxygen migration in $HfO_2$ gate dielectricis is 0.24eV, which can explain a leakage origin of gate dielectric.

• 전자공학회논문지A
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• 제30A권2호
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• pp.76-85
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• 1993

This paper describes the design of a technology-independent logic, function, and timing extraction system from SPICE-like network descriptions. Technology-independent extraction mechanism is provided in the form of technology files containing the rules for constructing logic gates and functional blocks. The designed system can be more effectively used in cell-based design by describing the cells to be extracted. Timing extraction is performed by using a linear RC gate delay model which takes interconnection delay into account. Experimental results show that estimated delay is within 10 percents for logic gate circuits when compared with SPICE. Through higher-level design descriptions obtained by extraction, design cycles can be considerably reduces.

• 반도체디스플레이기술학회지
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• 제19권3호
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• pp.68-72
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• 2020

A new method for array testing of TFT-CD panel with the integrated gate driver circuits is presented. As larger size/high resolution TFT-LCD with the peripheral driver circuits has emerged, one of the important problems for manufacturing is array testing on the panel. This paper describes the technology of detecting defective arrays and optimizing the array testing process. For the effective characterization of pixel array, the pixel storage capability is simulated and measured with voltage imaging system. This technology permits full functional testing during the manufacturing process, enabling fabrication of large TFT-LCD panels with the integrated driver circuits.

• 진공이야기
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• 제2권2호
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• pp.17-23
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• 2015

Medium Energy Ion Scattering (MEIS) has been successfully used for ultrathin film analysis such as gate oxides and multilayers due to its single atomic depth resolution in compostional and structural depth profiling. Recently, we developed a time-of-flight (TOF) MEIS for the first time, which can analyze a $10{\mu}m$ small spot. Small spot analysis would be useful for test pattern analysis in semiconductor industry and various thin film technology. The ion beam damage problem is minimized due to its improved collection efficiency by orders of magnitude and the ion beam neutralization problem is removed completely for quantitative analysis. Newly developed TOF-MEIS has been applied for gate oxides, ultra shallow junctions, nanoparticles, FINFET structures to provide compositional and structural profiles. Further development for submicron spot analysis and applications for functional nano thin films and nanostructured materials are expected for various nanotechnology and biotehnology.

• 한국전자통신학회논문지
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• 제9권4호
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• pp.447-454
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• 2014

최근에 양자회로 합성과 관련한 대부분의 방법들은 컴퓨터 시뮬레이션에 적합한 서술적 표현 구조를 채택하고 있어 합성된 양자함수들에 대한 분석이 어렵다. 본 논문에서는 구조가 단순하고 직관적 사고가 가능한 양자회로의 새로운 함수표현법을 제안한다. 본 논문 제안사항은 타깃라인상의 유니터리 연산자들의 직렬 적 행렬연산을 멱함수의 산술연산과 modulo 2 연산이란 수학적 치환을 통해 유니터리 연산자의 제어입력을 자신의 멱함수로 합성하는 새로운 함수합성에 있다. 본 논문의 함수합성 알고리듬은 의사-제어된 NCV-양자게이트를 이용한 가역 및 비가역 양자회로들의 함수표현과 새로운 함수합성에 유용하다.

• 한국환경과학회지
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• 제25권4호
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• pp.491-504
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• 2016

This study, examines the flow characteristics of upstream channel depending on water gate operation of Nakdan Multi-fuctional weir. The specific purpose of this study are to simulate the variation of flow velocity depending on the operation of the weir using 1-dimensional hydraulic model, HEC-RAS, and compare it with observed velocity. For discharge conditions from $50m^3/s$ to $3,500m^3/s$, it is observed that the velocity of upstream channel is almost constant, whereas for probability flood discharge, the velocity and froude number are increased as the discharge values are increased. The velocity values for downstream boundary condition EL, 40.0 m are more decreased than those for EL. 40.5m. From comparison on the variation of water stage depending on water gate operation, it is observed that the stage values are almost constant for discharges below $300m^3/s$, whereas 5 cm to 20 cm for discharges over $700m^3/s$. Flow velocity at streamflow gauging station. Nakdong, is decreased by more than 875% after installing the weir. The results obtained from this study indicate that the velocity of upstream channel is decreased and the discharge and velocity of downstream channel are significantly varied after installing the weir.