• 제목/요약/키워드: functional gate

검색결과 118건 처리시간 0.045초

Scaling Rules for Multi-Finger Structures of 0.1-μm Metamorphic High-Electron-Mobility Transistors

  • Ko, Pil-Seok;Park, Hyung-Moo
    • Journal of electromagnetic engineering and science
    • /
    • 제13권2호
    • /
    • pp.127-133
    • /
    • 2013
  • We examined the scaling effects of a number of gate_fingers (N) and gate_widths (w) on the high-frequency characteristics of $0.1-{\mu}m$ metamorphic high-electron-mobility transistors. Functional relationships of the extracted small-signal parameters with total gate widths ($w_t$) of different N were proposed. The cut-off frequency ($f_T$) showed an almost independent relationship with $w_t$; however, the maximum frequency of oscillation ($f_{max}$) exhibited a strong functional relationship of gate-resistance ($R_g$) influenced by both N and $w_t$. A greater $w_t$ produced a higher $f_{max}$; but, to maximize $f_{max}$ at a given $w_t$, to increase N was more efficient than to increase the single gate_width.

Electrical transport characteristics of deoxyribonucleic acid conjugated graphene field-effect transistors

  • Hwang, J.S.;Kim, H.T.;Lee, J.H.;Whang, D.;Hwang, S.W.
    • 한국진공학회:학술대회논문집
    • /
    • 한국진공학회 2011년도 제40회 동계학술대회 초록집
    • /
    • pp.482-483
    • /
    • 2011
  • Graphene is a good candidate for the future nano-electronic materials because it has excellent conductivity, mobility, transparency, flexibility and others. Until now, most graphene researches are focused on the nano electronic device applications, however, biological application of graphene has been relatively less reported. We have fabricated a deoxyribonucleic acid (DNA) conjugated graphene field-effect transistor (FET) and measured the electrical transport characteristics. We have used graphene sheets grown on Ni substrates by chemical vapour deposition. The Raman spectra of graphene sheets indicate high quality and only a few number of layers. The synthesized graphene is transferred on top of the substrate with pre-patterned electrodes by the floating-and-scooping method [1]. Then we applied adhesive tapes on the surface of the graphene to define graphene flakes of a few micron sizes near the electrodes. The current-voltage characteristic of the graphene layer before stripping shows linear zero gate bias conductance and no gate operation. After stripping, the zero gate bias conductance of the device is reduced and clear gate operation is observed. The change of FET characteristics before and after stripping is due to the formation of a micron size graphene flake. After combined with 30 base pairs single-stranded poly(dT) DNA molecules, the conductance and gate operation of the graphene flake FETs become slightly smaller than that of the pristine ones. It is considered that DNA is to be stably binding to the graphene layer due to the ${\pi}-{\pi}$ stacking interaction between nucleic bases and the surface of graphene. And this binding can modulate the electrical transport properties of graphene FETs. We also calculate the field-effect mobility of pristine and DNA conjugated graphene FET devices.

  • PDF

저항성 단락과 개방 결함을 갖는 메모리에 대한 동작분석과 효율적인 테스트 알고리즘에 관한 연구 (A study on behavioral analysis and efficient test algorithm for memory with resistive short and open defects)

  • 김대익;배성환;이상태;이창기;전병실
    • 전자공학회논문지B
    • /
    • 제33B권7호
    • /
    • pp.70-79
    • /
    • 1996
  • To increase the functionality of the memories, previous studies have deifned faults models and proposed functional testing algorithms with low complexity. Although conventional testing depended strongly on functional (voltage) testing method, it couldn't detect short and open defects caused by gate oxide short and spot defect which can afect memory reliability. Therefore, IDDQ (quiescent power supply current) testing is required to detect defects and thus can obtain high reliability. In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in mOS FET and observe behavior of the memory by analyzing voltage at storge nodes of the memory and IDDQ resulting from PSPICE simulation. Finally, using this behavioral analysis, we propose a linear testing algorithm of complexity O(N) which can be applicable to both functional testing and IDDQ testing simultaneously to obtain high functionality and reliability.

  • PDF

다기능보의 수문운영에 따른 금강의 장기하상변동 및 홍수위변화 분석 (Analysis of Long-Term Riverbed-Level and Flood Stage Variation due to Water Gate Operation of Multi-functional Weirs at Geum River)

  • 정안철;정관수
    • 한국수자원학회논문집
    • /
    • 제48권5호
    • /
    • pp.379-391
    • /
    • 2015
  • 국내 4대강에 설치된 다기능보는 하천을 횡단하는 수공구조물로써 고정보와 가동보로 구분되어 설치되었으며, 각 다기능보의 수문운영 방식에 따라 유량이 변화하여 하상변동 및 유사이동 형태의 변화 가능성이 있다. 본 연구에서는 다기능보의 수문운영에 따른 장기 하상변동을 금강유역을 중심으로 연구하였다. 연구결과, 금강에서는 다기능보의 설치 및 수문운영 시나리오에 따라서 최심하상고의 변화가 연평균하상고의 변화에 비해서 상대적으로 큰 것으로 나타났다. 최심하상고의 하상저하는 최대 2.79 m, 하상상승은 최대 1.90 m까지 발생하는 것으로 나타났으며, 연평균하상고의 하상저하는 최대 2.16 m, 하상상승은 최대 1.24 m까지 발생하는 것으로 나타났다. 또한 하상변동에 따른 홍수위 분석 결과, 다기능보 설치 후에 홍수위가 대부분 상승하는 것으로 나타났으며, 최대 2.23 m까지 상승하는 것으로 나타났다. 이러한 결과로 인해서 제방의 여유고를 상회하는 홍수위가 발생할 가능성이 있기 때문에, 하천의 유사관리 및 하천계획수립을 함에 있어서 다기능보의 수문운영을 고려해야 한다고 판단된다. 또한 본 연구결과는 향후 하천계획을 수립함에 있어서 종단적 하도관리 및 안정하상 채택 등을 위해서 기초자료로 활용될 수 있을 것으로 본다.

게이트 및 기능 레벨 논리 시뮬레이터 (A Gate and Functional Level Logic Simulator)

  • 박홍준;김종성;조순복;신용철;임인칠
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
    • /
    • pp.1577-1580
    • /
    • 1987
  • This paper proposes a gate and functional level logic simulator which can be run on XENIX O.S. The simulator has hierarchical structure including Hardware Description Language compiler, Waveform Description Language compiler, and Simulation Command Language compiler. The Hardware Description Language compiler generates data structure composed of gate structure, wire structure, condition structure, and event structure. Simulation algorithm is composed of selective trace and event-driven methods. To improve simulation speed, Cross Referenced Linked List Structure ia defined in building the data structure of circuits.

  • PDF

스위칭 네트워크와 디지털 접선 장치에서의 CMOS 게이트 어레이 IC 적용 (An Application of CMOS Gate Array Integrated Circuits to Switching Network and Digital Line Concentrator)

  • 박항구;박권철;조용현
    • 대한전자공학회논문지
    • /
    • 제24권4호
    • /
    • pp.652-657
    • /
    • 1987
  • This paper describes an application of CMOS Gate Array Integrated Cricuits to the implementation of three functional units: A Multiplexer, Time Switch, and Demultiplexer in the Switching Network and Digital Line Concentrator of TDX-1 system, which is a fully digital time division electronic switching system in Korea. The application of CMOS Gate Array Integrated Circuits significantly improves the overall system performance in terms of power consumption, cost, size, reliability, and timing margin, etc.

  • PDF

Transparent and Flexible All-Organic Multi-Functional Sensing Devices Based on Field-effect Transistor Structure

  • Trung, Tran Quang;Tien, Nguyen Thanh;Seol, Young-Gug;Lee, Nae-Eung
    • 한국진공학회:학술대회논문집
    • /
    • 한국진공학회 2011년도 제40회 동계학술대회 초록집
    • /
    • pp.491-491
    • /
    • 2011
  • Transparent and flexible electronic devices that are light-weight, unbreakable, low power consumption, optically transparent, and mechanical flexible possibly have great potential in new applications of digital gadgets. Potential applications include transparent displays, heads-up display, sensor, and artificial skin. Recent reports on transparent and flexible field-effect transistors (tf-FETs) have focused on improving mechanical properties, optical transmittance, and performances. Most of tf-FET devices were fabricated with transparent oxide semiconductors which mechanical flexibility is limited. And, there have been no reports of transparent and flexible all-organic tf-FETs fabricated with organic semiconductor channel, gate dielectric, gate electrode, source/drain electrode, and encapsulation for sensor applications. We present the first demonstration of transparent, flexible all-organic sensor based on multifunctional organic FETs with organic semiconductor channel, gate dielectric, and electrodes having a capability of sensing infrared (IR) radiation and mechanical strain. The key component of our device design is to integrate the poly(vinylidene fluoride-triflouroethylene) (P(VDF-TrFE) co-polymer directly into transparent and flexible OFETs as a multi-functional dielectric layer, which has both piezoelectric and pyroelectric properties. The P(VDF-TrFE) co-polumer gate dielectric has a high sensitivity to the wavelength regime over 800 nm. In particular, wavelength variations of P(VDF-TrFE) molecules coincide with wavelength range of IR radiation from human body (7000 nm ~14000 nm) so that the devices are highly sensitive with IR radiation of human body. Devices were examined by measuring IR light response at different powers. After that, we continued to measure IR response under various bending radius. AC (alternating current) gate biasing method was used to separate the response of direct pyroelectric gate dielectric and other electrical parameters such as mobility, capacitance, and contact resistance. Experiment results demonstrate that the tf-OTFT with high sensitivity to IR radiation can be applied for IR sensors.

  • PDF

Thermo-Sensitive Polyurethane Membrane with Controllable Water Vapor Permeation for Food Packaging

  • Zhou, Hu;Shit, Huanhuan;Fan, Haojun;Zhou, Jian;Yuan, Jixin
    • Macromolecular Research
    • /
    • 제17권7호
    • /
    • pp.528-532
    • /
    • 2009
  • The size and shape of free volume (FV) holes available in membrane materials control the rate of gas diffusion and its permeability. Based on this principle, a segmented, thermo-sensitive polyurethane (TSPU) membrane with functional gate, i.e., the ability to sense and respond to external thermo-stimuli, was synthesized. This smart membrane exhibited close-open characteristics to the size of the FV hole and water vapor permeation and thus can be used as smart food packaging materials. Differential scanning calorimetry (DSC), dynamic mechanical analysis (DMA), positron annihilation lifetimes (PAL) and water vapor permeability (WVP) were used to evaluate how the morphological structure of TSPU and the temperature influence the FV holes size. In DSC and DMA studies, TSPU with a crystalline transition reversible phase showed an obvious phase-separated structure and a phase transition temperature at $53^{\circ}C$ (defined as the switch temperature and used as a functional gate). Moreover, the switch temperature ($T_s$) and the thermal-sensitivity of TSPU remained available after two or three thermal cyclic processes. The PAL study indicated that the FV hole size of TSPU is closely related to the $T_s$. When the temperature varied cyclically from $T_s-10{\circ}C$ to $T_s+10^{\circ}C$, the average radius (R) of the FV holes of the TSPU membrane also shifted cyclically from 0.23 to 0.467 nm, exhibiting an "open-close" feature. As a result, the WVP of the TSPU membrane also shifted cyclically from 4.30 to $8.58\;kg/m^2{\cdot}d$, which produced an "increase-decrease" response to the thermo-stimuli. This phase transition accompanying significant changes in the FV hole size and WVP can be used to develop "smart materials" with functional gates and controllable water vapor permeation, which support the possible applications of TSPU for food packaging.

Organic Thin Film Transistors with Gate Dielectrics of Plasma Polymerized Styrene and Vinyl Acetate Thin Films

  • Lim, Jae-Sung;Shin, Paik-Kyun;Lee, Boong-Joo
    • Transactions on Electrical and Electronic Materials
    • /
    • 제16권2호
    • /
    • pp.95-98
    • /
    • 2015
  • Organic polymer dielectric thin films of styrene and vinyl acetate were prepared by the plasma polymerization deposition technique and applied for the fabrication of an organic thin film transistor device. The structural properties of the plasma polymerized thin films were characterized by Fourier-transform infrared spectroscopy, X-ray diffraction, atomic force microscopy, and contact angle measurement. Investigation of the electrical properties of the plasma polymerized thin films was carried out by capacitance-voltage and current-voltage measurements. The organic thin film transistor device with gate dielectric of the plasma polymerized thin film revealed a low operation voltage of −10V and a low threshold voltage of −3V. It was confirmed that plasma polymerized thin films of styrene and vinyl acetate could be applied to functional organic thin film transistor devices as the gate dielectric.