• JSTS:Journal of Semiconductor Technology and Science
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• 제3권4호
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• pp.217-222
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• 2003

A new two-dimensional analytical model for the potential distribution and drain-induced barrier lowering (DIBL) effect of fully depleted short-channel Silicon-on-insulator (SOI)-MESFET's has been presented in this paper. The two dimensional potential distribution functions in the active layer of the device is approximated as a simple parabolic function and the two-dimensional Poisson's equation has been solved with suitable boundary conditions to obtain the bottom potential at the Si/oxide layer interface. It is observed that for the SOI-MESFET's, as the gate-length is decreased below a certain limit, the bottom potential is increased and thus the channel barrier between the drain and source is reduced. The similar effect may also be observed by increasing the drain-source voltage if the device is operated in the near threshold or sub-threshold region. This is an electrostatic effect known as the drain-induced barrier lowering (DIBL) in the short-gate SOI-MESFET's. The model has been verified by comparing the results with that of the simulated one obtained by solving the 2-D Poisson's equation numerically by using the pde toolbox of the widely used software MATLAB.

• 대한전자공학회논문지SD
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• 제45권7호
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• pp.9-16
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• 2008

본 논문에서는 short-gate SOI MESFET의 문턱전압 도출을 위한 간단한 해석적 모델을 제시하였다. 완전 공핍된 실리콘 채널 영역에서는 2차원 Poisson 방정식을, buried oxide 영역에서는 2차원 Laplace 방정식을 반복법(iteration method)을 이용해 풀어 각 영역 내에서의 전위 분포를 채널에 수직한 방향의 좌표에 대해 5차 다항식으로 표현하였으며 채널 바닥 전위를 구하였다. 채널 바닥 전위의 최소치가 0이 되는 게이트 전압을 문턱 전압으로 제안하여 closed-form의 문턱 전압 식을 도출하였다. 도출된 문턱 전압 표현 식을 모의 실험한 결과, 소자의 구조 parameter와 가해진 bias 전압에 대한 정확한 의존성을 확인할 수 있었다.

• 대한전자공학회논문지SD
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• 제44권7호통권361호
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• pp.16-23
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• 2007

본 논문에서는 완전 공핍된 SOI형 대칭 이중게이트 MOSFET의 문턱 전압에 대한 간단한 해석적 모델을 제시하고자 실리콘 몸체 내의 전위 분포를 근사적으로 채널에 수직한 방향의 좌표에 대해 4차 다항식으로 가정하였다. 이로써 2차원 포아송 방정식을 풀어 표면 전위의 표현식을 도출하고, 이 결과로부터 드레인 전압 변화에 의한 문턱 전압의 roll-off를 비교적 정확하게 기술할 수 있는 문턱 전압의 표현식을 closed-form의 간단한 표현식으로 도출하였다. 도출된 표현식으로 모의 실험을 수행한 결과 $0.01\;[{\mu}m]$의 실리콘 채널 길이 범위까지 채널 길이에 지수적으로 감소하는 것을 보이는 비교적 정확한 결과를 얻을 수 있음을 확인하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.918-921
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• 1999

The breakdown voltage in fully depleted SOI N-MOSFET’s have been studied over a wide range of film thicknesses, channel doping, and channel lengths. An asynmmetric Source/Drain SOI technology is proposed, which having the advantages of Normal LDD SOI(Silicon-On-Insulator) for breakdown voltage and gives a high drivability of LDD SOI without sacrificings hot carrier immunity The two-dimensional simulations have been used to investigate the breakdown behavior in these device. It is found that the breakdown voltage(BVds) is almost same with high current drivability as that in Normal LDD SOI device structure.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.35-35
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• 2009

Capacitorless one transistor dynamic random access memory (1T-DRAM) cells were fabricated on the fully depleted strained-silicon-on-insulator (FD sSOI) and the effects of silicon back interface state on buried oxide (BOX) layer on the memory properties were evaluated. As a result, the fabricated 1T-DRAM cells showed superior electrical characteristics and a large sensing current margin (${\Delta}I_s$) between "1" state and "0" state. The back interface of SOI based capacitorless 1T-DRAM memory cell plays an important role on the memory performance. As the back interface properties were degraded by increase rapid thermal annealing (RTA) process, the performance of 1T-DRAM was also degraded. On the other hand, the properties of back interface and the performance of 1T-DRAM were considerably improved by post RTA annealing process at $450^{\circ}C$ for 30 min in a 2% $H_2/N_2$ ambient.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 학술대회지
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• pp.482-485
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• 2004

We fabricated a hybrid bulk/fully depleted silicon on insulator (FDSOI) complementary metal oxide semiconductor (CMOS) active pixel image sensor. The active pixel is comprised of reset and source follower transistors on the SOI seed wafer, while the pinned photodiode and readout gate and floating diffusion are fabricated on the SOI handle wafer after the removal of the buried oxide. The source of dark current is eliminated by hybrid bulk/FDSOI pixel structure between localized oxidation of silicon (LOCOS) and photodiode(PD). By using the low noise hybrid pixel structure, dark currents qm be suppressed significantly. The pinned photodiode can also be optimized for quantum efficiency and reduce the noise of dark current. The spectral response of the pinned photodiode on the SOI handle wafer is very flat between 400 nm and 700 nm and the dark current that is higher than desired is about 10 nA/cm2 at a $V_{DD}$ of 2 V.

• ETRI Journal
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• 제26권6호
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• pp.575-582
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• 2004

Fully-depleted silicon-on-insulator (FD-SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the single- raised (SR) and double-raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self-heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self-heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a $1.1\;{\mu}m^2$ 6T-SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra-thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.

• 대한전자공학회논문지SD
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• 제42권9호
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• pp.9-18
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• 2005

60 nm C-MOSFET 기술 분기점 이상의 고성능, 저전력 트랜지스터를 구현 시키기 위해 SiGe/SiO2/Si위에 성장된 strained Si의 두께가 전자 이동도에 미치는 영향을 두 가지 관점에서 조사 연구하였다. 첫째, inter-valley phonon 산란 모델의 매개변수들을 최적화하였고 둘째, strained Si 반전층의 2-fold와 4-fold의 전자상태, 에너지 밴드 다이어그램, 전자 점유도, 전자농도, phonon 산란율과 phonon-limited 전자이동도를 이론적으로 계산하였다. SGOI n-MOSFET의 전자이동도는 고찰된 SOI 구조의 Si 두께 모든 영역에서 일반적인 SOI n-MOSFET보다 $1.5\~1.7$배가 높음이 관찰 되었다. 이러한 경향은 실험 결과와 상당히 일치한다. 특히 strained Si의 두께가 10 nm 이하일 때 Si 채널 두께가 6 nm 보다 작은 SGOI n-MOSFET에서의 phonon-limited 전자 이동도는 일반 SOI n-MOSFET과 크게 달랐다. 우리는 이러한 차이가 전자들이 suained SGOI n-MOSFET의 반전층에서 SiGe층으로 터널링 했기 때문이고, 반면에 일반 SOI n-MOSFET에서는 캐리어 confinement 현상이 발생했기 때문인 것으로 해석하였다. 또한 우리는 10 nm와 3 nm 사이의 Si 두께에서는 SGOI n-MOSFET의 phonon-limited 전자 이동도가 inter-valley phonon 산란율에 영향을 받는 다는 것을 확인하였으며, 이러한 결과는 더욱 높은 드레인 전류를 얻기 위해서 15 nm 미만의 채널길이를 가진 완전공핍 C-MOSFET는 stained Si SGOI 구조로 제작하여야 함을 확인 했다

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.8-22
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• 2014

In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (VTH) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted silicon-on-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmented-channel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.