• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.1-11
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• 1997

We developed a base station modulator ASIC for CDMA digital cellular system. In CDMA digital cellular system, the modulation is performed by convolutional encoding and QPSK with spread spectrum. The function blocks of base station modulator are CRC, convolutional encoder, interleaver pseudo-moise scrambler, power control bit puncturing, walsh cover, QPSK, gain controller, combiner and multiplexer. Each function block was designed by the logic synthesis of VHDL codes. The VHDL code was described at register transfer level and the size of code is about 8,000 lines. The circuit simulation and logic simulation were performed by COMPASS tools. The chip (ES-C2212B CMB) contains 25,205 gates and 3 Kbit SRAM, and its chip size is 5.25 mm * 5,45 mm in 0.8 mm CMOS cell-based design technology. It is packaged in 68 pin PLCC and the power dissipation at 10MHz is 300 mW at 5V. The ASIC has been fully tested and successfully working on the CDMA base station system.

• Journal of the Korean Society of Industry Convergence
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• v.21 no.6
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• pp.265-271
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• 2018

DC-DC buck converter is a critical building block in the power management integrated circuit (PMIC) architecture for the portable devices such as cellular phone, personal digital assistance (PDA) because of its power efficiency over a wide range of conversion ratio. To ensure a safe operation, avoid unexpected damages and enhance the reliability of the converter, fully-integrated protection circuits such as over voltage protection (OVP), under voltage lock out (UVLO), startup, and thermal shutdown (TSD) blocks are designed. In this paper, these three fully-integrated protection circuit blocks are proposed for use in the DC-DC buck converter. The buck converter with proposed protection blocks is operated with a switching frequency of 1 MHz in continuous conduction mode (CCM). In order to verify the proposed scheme, the buck converter has been designed using a 180 nm CMOS technology. The UVLO circuit is designed to track the input voltage and turns on/off the buck converter when the input voltage is higher/lower than 2.6 V, respectively. The OVP circuit blocks the buck converter's operation when the input voltage is over 3.3 V, thereby preventing the destruction of the devices inside the controller IC. The TSD circuit shuts down the converter's operation when the temperature is over $85^{\circ}C$. In order to verify the proposed scheme, these protection circuits were firstly verified through the simulation in SPICE. The proposed protection circuits were then fabricated and the measured results showed a good matching with the simulation results.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.355-359
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• 2001

This paper presents an implementation of digital control system of speed sensorless for Reluctance Synchronous Motor (RSM) drives with DTC. The control system consists of stator flux observer, rotor position/speed/torque estimator, two hysteresis band controllers, an optimal switching look-up table, IGBT voltage source inverter, and TMS320C31 DSP controller by using fully integrated control software. The stator flux observer is based on the combined voltage and current model with stator flux feedback adaptive control that inputs are current and voltage sensing of motor terminal with estimated rotor angle for wide speed range. The rotor position is estimated by observed stator flux-linkage space vector. The estimated rotor speed is determined by differentiation of the rotor position used only in the current model part of the flux observer for a low speed operating area. It does not require the knowledge of any motor parameters, nor particular care for motor starting, In order to prove the suggested control algorithm, we have a simulation and testing at actual experimental system. The developed sensorless control system is shown a good speed control response characteristic results and high performance features in 50/1000 rpm with 1.0Kw RSM having 2.57 ratio of d/q reluctance.

• Proceedings of the KIPE Conference
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• 2001.12a
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• pp.23-26
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• 2001

This paper presents a digital motion control system for Reluctance Synchronous Motor (RSM) drives with direct torque control (DTC). The system consists of stator flux observer, torque estimator: two hysteresis band controllers, an optimal switching look-up table, IGBT voltage source inverter(VSI), and TMS320C31 DSP controller by using fully integrated control software. The stator flux observer is based on the combined voltage and current model with stator flux feedback adaptive control of which inputs are current, voltage and actual rotor angle for wide speed range. In order to prove the suggested motion control algorithm, There are some simulation and testing at actual experimental system. The developed digitally high-performance motion control system are shown a good motion control response characteristic results and high performance features using 1.0Kw RSM.

• Journal of Electrical Engineering and Technology
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• v.3 no.4
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• pp.528-537
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• 2008

Primary frequency control(PFC) has the ability to regulate short period random variations of frequency during normal operation conditions and also to respond rapidly to emergencies. However, during the past decade, numerous significant sized blackouts occurred worldwide that resulted in serious economic losses. Therefore, the conclusion has been reached that the ability of the current PFC to meet an emergency is poor, and security of power systems should be improved. An alternative to enhance the PFC and thus security is to store excessive amounts of energy during off-peak load periods in efficient energy storage systems for substituting the primary control reserve. In this sense, superconducting magnetic energy storage(SMES) in combination with a static synchronous compensator(STATCOM) is capable of supplying power systems with both active and reactive powers simultaneously and very rapidly, and thus is able to enhance the security dramatically. In this paper, a new concept of PFC based on incorporating a STATCOM-SMES is presented. A complete detailed model is proposed and a new control scheme is designed, comprising an enhanced frequency control scheme, and a fully decoupled current control strategy in d-q coordinates with a novel controller to prevent dc bus capacitors voltage drift/imbalance. The performance of the proposed control schemes is validated through digital simulation carried out using MATLAB/Simulink.

• ETRI Journal
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• v.31 no.6
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• pp.770-777
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• 2009

We have developed a fully functional reconfigurable optical add-drop multiplexer (ROADM) switch module using a polymer integrated photonic lightwave circuit technology. The polymer variable optical attenuator (VOA) array and digital optical switch array are integrated into one polymer PLC chip and packaged to form a 10-channel VOA integrated optical switch module. Four of these optical switch modules are used in the ROADM switch module to execute 40-channel switching and power equalization. As a wavelength division multiplexer (WDM) filter device, two C-band 40-channel athermal arrayed waveguide grating WDMs are used in the ROADM module. Optical power monitoring of each channel is carried out using a 5% tap PD. A controller and firmware having the functions of a 40-channel switch and VOA control, optical power monitoring, as well as TEC temperature control, and data communication interfaces are also developed in this study.

• Proceedings of the KIEE Conference
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• 2001.10a
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• pp.161-164
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• 2001

This paper presents a digital speed sensorless control system for Reluctance Synchronous Motor (RSM) drives with direct torque control (DTC). The system consist of stator flux observer, rotor speed estimator, torque estimator two hysteresis band controllers, an optimal switching look-up table. IGBT voltage source inverter, and TMS320C31DSP controller by using fully integrated control software. The stator flux observer is based on the combined voltage and current model with stator flux feedback adaptive control that inputs are current and voltage sensing of motor terminal with estimated rotor angle for wide speed range. The rotor speed is estimated by the observed stator flux-linkage space vector. The estimated rotor speed can be determinated by differentiation of the rotor position used only in the current model part of the flux observer for a low speed operating area. In order to prove the suggested speed sensorless control algorithm. There are some simulation and testing at actual experimental system. The developed digitally high- performance speed sensorless control system are shown a good speed control response characteristic results and high Performance features using 1.0Kw RSM.

• Journal of the HCI Society of Korea
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• v.12 no.1
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• pp.5-13
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• 2017

Interactive intervention of the human presenter is one of the important factors that make the visualization more effective. Rather than just showing the content, the presenter enhances the process of the information delivery by providing the context of visualization. In this paper, we define this as an augmented presentation. In augmented presentation concept, the presenter can facilitate presentation more actively by being fully immersed in the visualization space and reaching and interacting into digital information. In order to concrete the concept, we design presentation space that enables the presenter to be seamlessly immersed in the visualization. Also we increase the presenter's roles as a storyteller, controller and augmenter allowing the presenter to fully support communicative process between the audience and the visualization. Then, we present an augmented presentation system to verify the proposed concept. We rendered 3D visualization through a half-mirror film and a wall projection screen that are place in parallel and applied with stereoscopic images, then, spatially align the presenter inside the virtual visualization space. After that, we conduct a controlled experiment to investigate the subjective level of immersion and engagement of the audience to HoloStation compared to traditional presentation system. Our initial investigation suggests that the newly conceived augmented presentation has potential not only to enhance the information presentation but also to supports the delivery of visualization.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.58-67
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• 2009

This paper presents a fully digital gain control system with a new high bandwidth and wide dynamic range power detector for DVB-S2 application. Because the peak-to-average power ratio (PAPR) of DVB-S2 system is so high and the settling time requirement is so stringent, the conventional closed-loop analog gain control scheme cannot be used. The digital gain control is necessary for the robust gain control and the direct digital interface with the baseband modem. Also, it has several advantages over the analog gain control in terms of the settling time and insensitivity to the process, voltage and temperature variation. In order to have a wide gain range with fine step resolution, a new AGC system is proposed. The system is composed of high-bandwidth digital VGAs, wide dynamic range power detectors with RMS detector, low power SAR type ADC, and a digital gain controller. To reduce the power consumption and chip area, only one SAR type ADC is used, and its input is time-interleaved based on four power detectors. Simulation and measurement results show that the new AGC system converges with gain error less than 0.25 dB to the desired level within $10{\mu}s$. It is implemented in a $0.18{\mu}m$ CMOS process. The measurement results of the proposed IF AGC system exhibit 80-dB gain range with 0.25-dB resolution, 8 nV/$\sqrt{Hz}$ input referred noise, and 5-dBm $IIP_3$ at 60-mW power consumption. The power detector shows the 35dB dynamic range for 100 MHz input.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.86-94
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• 2012

In this paper we propose a hardware architecture of high-speed CGH (computer generated hologram) generation processor, which particularly reduces the number of memory access times to avoid the bottle-neck in the memory access operation. For this, we use three main schemes. The first is pixel-by-pixel calculation rather than light source-by-source calculation. The second is parallel calculation scheme extracted by modifying the previous recursive calculation scheme. The last one is a fully pipelined calculation scheme and exactly structured timing scheduling by adjusting the hardware. The proposed hardware is structured to calculate a row of a CGH in parallel and each hologram pixel in a row is calculated independently. It consists of input interface, initial parameter calculator, hologram pixel calculators, line buffer, and memory controller. The implemented hardware to calculate a row of a $1,920{\times}1,080$ CGH in parallel uses 168,960 LUTs, 153,944 registers, and 19,212 DSP blocks in an Altera FPGA environment. It can stably operate at 198MHz. Because of the three schemes, the time to access the external memory is reduced to about 1/20,000 of the previous ones at the same calculation speed.