• Spatial Information Research
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• v.8 no.1
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• pp.171-182
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• 2000

Random sampling or systematic sampling method is commonly used to assess the accuracy of classification results. In remote sensing, with these sampling method, much time and tedious works are required to acquire sufficient ground truth data. So , a more effective sampling method that can retain the characteristics of the population is required. In this study, fractal analysis is adopted as an index for reference sampling . The fractal dimensions of the whole study area and the sub-regions are calculated to choose sub-regions that have the most similar dimensionality to that of whole-area. Then the whole -area s classification accuracy is compared to those of sub-regions, respectively, and it is verified that the accuracies of selected sub regions are similar to that of full-area . Using the above procedure, a new kind of reference sampling method is proposed. The result shows that it is possible to reduced sampling area and sample size keeping up the same results as existing methods in accuracy tests. Thus, the proposed method is proved cost-effective for reference data sampling.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.3
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• pp.106-111
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the parallel operations and SAD unit control using pattern information, the proposed IME instruction supports not only full search algorithm but also other fast search algorithms. The hardware size is 77K gates for each Processing Element Group (PEG) which has 256 SAD PEs. The proposed ASIP runs at 160MHz with sixteen PEGs and it can handle 1080p@30 frame in real time.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.219-225
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• 2014

This paper describes an IC for Power Factor Correction. It can use electrical appliances which convert power from AC to DC. The power factor can be influenced not only phase difference of voltage and current but also sudden change of current waveform. This circuit enables current wave supplied to load by close to sinusoidal and minimum phase difference of voltage and current waveform. A self oscillated 10[kHz]~100[kHz] pulse signal converted to PWM waveform and it chops rectified full wave AC power which flows to load device. The multiplier and zero current detector circuit, UVLO, OVP, BGR circuits were designed. This IC has been designed and whole chip simulation use 0.5[um] double poly, double metal 20[V] CMOS process.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.11-19
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• 2014

In this paper, a low complexity parallel sphere decoder algorithm is proposed for high-order MIMO system. It reduces the computational complexity compared to the fixed-complexity sphere decoder (FSD) algorithm by static tree-pruning and dynamic tree-pruning using scalable node operators, and offers near-maximum likelihood decoding performance. Moreover, it also offers hardware-friendly node operation algorithm through fixing the variable computational complexity caused by the sequential nature of the conventional SD algorithm. A Monte Carlo simulation shows our proposed algorithm decreases the average number of expanded nodes by 55% with only 6.3% increase of the normalized decoding time compared to a full parallelized FSD algorithm for high-order MIMO communication system with 16 QAM modulation.

• Journal of the Korea Society of Computer and Information
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• v.11 no.6 s.44
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• pp.261-267
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• 2006

In order to perform a probabilistic safety assessment (PSA), it requires a large number of data for various fields. And the quality of a PSA results have become more important thing of the risk assessment. As part of enhancing the PSA qualify, Korea Atomic Energy Research Institute is developing a full power Human Reliability Analysis (HRA) calculator to manage human failure events (HFEs) and to calculate the diagnosis human error probabilities and execution human error probabilities. This paper introduces the development process and an overview of a standard HRA method for nuclear power plants. The study was carried out in three stages; 1) development of the procedures and rules for a standard HRA method. 2) design of a system structure, 3) development of the HRA calculator.

• Journal of the Korean BIBLIA Society for library and Information Science
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• v.26 no.1
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• pp.217-231
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• 2015

This study aims to infer the gene-protein 'brings_about' chains of pancreatic cancer which were referred to in the pancreatic cancer related researches by constructing the gene-protein interaction network of pancreatic cancer. The chains can help us uncover publicly unknown knowledge that would develop as empirical studies for investigating the cause of pancreatic cancer. In this study, we applied a novel approach that grafts text mining and the main path analysis into Swanson's ABC model for expanding intermediate concepts to multi-levels and extracting the most significant path. We carried out text mining analysis on the full texts of the pancreatic cancer research papers published during the last ten-year period and extracted the gene-protein entities and relations. The 'brings_about' network was established with bio relations represented by bio verbs. We also applied main path analysis to the network. We found the main direct 'brings_about' path of pancreatic cancer which includes 14 nodes and 13 arcs. 9 arcs were confirmed as the actual relations emerged on the related researches while the other 4 arcs were arisen in the network transformation process for main path analysis. We believe that our approach to combining text mining analysis with main path analysis can be a useful tool for inferring undiscovered knowledge in the situation where either a starting or an ending point is unknown.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.4
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• pp.984-995
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• 1996

Data errors according to the various noises caused in the satellite communication links are corrected by the Viterbi decoding algorithm which has extreme error correcting capability. In this paper, we designed and implemented a convolutional encoder and Viterbi decoder ASIC which is used to encode the input data at the transmit side and correct the errors of the received data at the receive side for use in the VSAT communication system. And this chip may be used in any BPSK, QPSK, or OQPSK transmission system. The ambiguity resolver corrects PSK modem ambiguities by delaying, interting, and/or exchanging code symbol to restore their original sequence and polarity. In case of previous decoding system, ambiguity state(AS) of data is resolved by external control logic and extra redundancy data are needed to resolve AS. But, by adopting decoder proposed in this paper, As of data is resolved automatically by internal logic of decoder in case of continuous mode, and by external As line withoug extra redudancy data in burst mode case. So, decoding parts are simple in continuous mode and transmission efficiency is increased in bust mode. The features of this chip are full duplex operation with independent transmit and receive control and clocks, start/stop inputs for use in burst mode systems, loopback function to verify encoder and decoder, and internal or external control to resolve ambinguity state. For verification of the function and performance of a fabricated ASIC chip, we equiped this chip in the Central and Remote Earth Station of VSAT system, and did the performance test using the commerical INTELSAT VII under the real satellite link environmens. The results of test were demonstrated the superiority of performance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.442-446
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• 2000

The metal-oxide-semiconductor field-effect transistor(MOSFET) has undergone many changes in the last decade in response to the constant demand for increased speed, decreased power, and increased parking density. Therefore, it was interested in scaling theory, and full-band Monte Carlo device simulator has been used to study the effects of device scaling on hot carriers in different MOSFET structures. MOSFET structures investigated in this study include a conventional MOSFET with a single source/drain, implant a lightly-doped drain(LDD) MOSFET, and a MOSFET built on an epitaxial layer(EPI) of a heavily-doped ground plane, and those are analyzed using TCAD(Technology Computer Aided Design) for scaling and simulation. The scaling has used a constant-voltage scaling method, and we have presented MOSFET´s characteristics such as I-V characteristic, impact ionization, electric field and recognized usefulness of TCAD, providing a physical basis for understanding how they relate to scaling.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.10
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• pp.2143-2149
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• 2012

DVB-S2 employs LDPC codes which approach to the Shannon's limit, since it has characteristics of a good distance, error floor does not appear. Furthermore it is possible to processes full parallel processing. However, it is very difficult to high speed decoding because of a large block size and number of many iterations. This paper present HSS algorithm to reduce the iteration numbers without performance degradation. In the flooding scheme, the decoder waits until all the check-to-variable messages are updated at all parity check nodes before computing the variable metric and updating the variable-to-check messages. The HSS algorithm is to update the variable metric on a check by check basis in the same way as one code draws benefit from the other. Eventually, LDPC decoding speed based on HSS algorithm improved 30% ~50% compared to conventional one without performance degradation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.519-521
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• 2011

NFC is enable communication between wireless davice within a distance of 10cm, one type of non-contanct short-range wireless communicaton using 13.56MHz frequency band. This is one type of RFID technology which include file transfer, contactless payment and RFID. NFC technology is standardized in 2003 already, it received much attention recently because NFC is announced full support in Android 2.3. And as APPLE is announced that have plan to monunt in iphone 5,mobile payment system is expected to change. Already SAMSUNG is launched NEXUS S mounted NFC chip and announced NFC chip will be mount GALAXY S2 LG Electronics is statemented NFC chip will be mount on smart phone that will realese this year. In this study, will announce about analysis for NFC technology and recently trend and used case.