• 한국정보통신학회논문지
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• 제13권3호
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• pp.531-536
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• 2009

본 논문에서는 개선된 회로를 적용한 $256{\times}256$ 픽셀 저항형 지문센서를 제안하고 있다. 단위 픽셀 수준의 센싱회로는 가변적인 전류를 전압으로 변환하여 이진 디지털 신호로 만든다. 정전기에 효과적으로 대처할 수 있는 인접 픽셀 간 전기적 차폐 레이아웃 구조를 제안하고 있다. 전체회로는 단위 센서 회로를 확장하여 ASIC 설계방식을 통하여 설계한 뒤 로직 및 회로에 대하여 모의실험을 하였다. 전체회로는 $0.35{\mu}m$ 표준 CMOS 공정규칙을 적용하여 센서블록은 전주문 방식을 적용하고 전체 칩은 자동배선 툴을 이용하여 반주문 방식으로 레이아웃을 실시하였다.

• 한국통신학회논문지
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• 제21권1호
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• pp.241-250
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• 1996

In this work, an improved architecture of two-dimensional digital filter(2D DF) is suggested, and then the filter is simulated by C, VHDL language and related layouts are designed by Berkeley CAD tools. The 2D DF consists of one-dimensional digital filters and delay lines. For one-dimensional digital filter(1D DF) case, once filter coefficients are represented by canonical signed digit formats, multiplications are exected by hardwired-shifting methods. The related bit numbers are handled to prevent picture quality degradation and pipelined adder architectures are adopted in each tap and output stage to speed up the filter. For delay line case, line-sharing DRAM is adopted to improve power dissipation and speed. The filter layout is designed by semi/full custom methods considering regularity and speed improvement, and normal operation is confirmed by simulation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 학술대회지
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• pp.836-841
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• 2004

This paper describes ASIC design for brightness revision control, A LED Pixel Matrix (LPM) design and LPM in natural color LED vision. A designed chip has 256 levels of gradation correspond to each Red, Green, Blue LED pixel respectively, which have received 8bit image data. In order to maintain color uniformity by reducing the original rank error of LED, we adjusted the specific character value 'a' and brightness revision value 'b' to pixel unit, module unit and LED vision respectively by brightness characteristic function with 'Y=aX+b'. In this paper, if designed custom chip and brightness revision control method are applied to manufacturing of natural color LED vision, we can obtain good quality of image. Furthermore, it may decrease the cost for manufacturing LED vision or installing the plants.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(4)
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• pp.139-142
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• 2000

In this paper, the ADI (Adaptive De-interlacing) algorithm is proposed, which improves visually and subjectively horizontal and vertical edges of the image processed by the ELA(Edge Line-based Average) method. This paper also proposes a VLSI architecture for the proposed algorithm and designed the architecture through the full custom CMOS layout process. The proposed algorithm is verified using C and Matlab and implemented using 0.6$\mu\textrm{m}$ 2-poly 3-metal CMOS standard libraries. For the circuit and logic simulation, Cadence tool is used.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1029-1032
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• 1998

In this paper, a comparative study is presented to evaluate the addition architecture of the high-speed checksum module in TCP/IP processing. In order to speed up TCP/IP processing, H/W implementation offers concurrent and parallel processing to yield high speed computation, with respect to S/W implementation. This research aims at comparing two addition architectures of checksum module, which is the major botteleneck in TCP/IP processing. The 16-bit and 8-bit byte-by-byte addition architecture are implemented by the full custom design, and compared, in analytical and experimental manner, from standpoint of space and performance. For LG $0.6\mu\textrm{m}$ TLM process, the 8-bit addition implementation requires the area, 1.3 times larger than the 16-bit one, and it operates at 80MHz while the 16-bit one runs by 66MHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1121-1124
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• 1998

A CMOS RF bandpass amplifier which performs both functions of low-noise amplifier and bandpass filter is designed for the application of 1.9 ㎓ RF front-end in wireless receivers. The positive-feedback Q-enhancement technique is used to overcome the low gain and low Q factor of the bandpass amplifier. The designed bandpass amplifier is simulated with HSPICE and fabricated using HYUNDAI $0.8\mu\textrm{m}$ CMOS 2-poly 2-metal full custom process. Under 3 V supply voltage, results of simulation show that the CMOS bandpass amplifier provides the power gain 23dB, noise figure 3.8 dB, and power dissipation 55mW.

• 전자공학회논문지C
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• 제35C권1호
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• pp.34-41
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• 1998

In this paper, I designed a P1394 serial bus chip as new bus interface architecture which can transmit the multimedia data at the rate of 400 Mbps and guarantee necessary bandwidth. because multimedia data become meaningless data after appropriate time, it is necessary to transfer multimedia data in real time, P1394 serial bus chip designed in this paper support isochronous transfer mode to solve this problem. Also, designed P1394 serial bus chip can transfer high quality video data or high quality audio data because it support the speed of 400 Mbps. While user must set device ID manually in previous interface such as SCSI, device ID is automatically determined if user connect each node with designed P1394 serial bus cable and power on. To design this chip, I verified the behavioral of the entrire system and synthesized layout. Also, I did layout the analog blocks and blocks which must be optimized in full custom.

• 전자공학회논문지B
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• 제32B권12호
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• pp.1644-1651
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• 1995

A data and clock recovery integrated circuit for MAC (Multiplexed Analog Component) TV standard is described. The chip performs the recovery of a system clock from a digitally encoded voice signal, clamping of a video signal for DC-level restoration, and precise gain control of a video signal in the presence of a large amplitude variation. A PLL (Phase Locked Loop) is used for timing recovery and a new gain control circuit is proposed which enhances its accuracy and dynamic range by employing two identical four-quadrant analog multipliers. The chip is designed in full custom with 1.5um BiCMOS technology, and layout verification is completed by post-simulation with the extracted circuit.

• 전자공학회논문지A
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• 제28A권1호
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• pp.60-73
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• 1991

This paper presents an efficient algorithm for incremental and hierarchical design rule checking of VLSI layouts, and describes the implementation of a layout editor using the proposed algorithm. Tracing the sliced edges divided by the intersection of the edges either ina polygon or in two polygons (Sliced-Edge Trace), the algorithm performs VLSI pattern operations like resizing and other Boolean operations. The algorithm is not only fast enough to check the layouts of full-custom designs in real-time, but is general enough to be used for arbitrarily shaped polygons. The proposed algorithm was employed in developingt a layout editor on engineering workstations running UNIX. The editor has been successfully used for checking, generating and resizing of VLSI layouts.

• 복식
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• 제15권
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• pp.47-54
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• 1990

Kyu-Soo Park wrote the book "Gur Ga Jap Bok Ko" (Proposition for Household Casuals) around A.D. 1865. He was a widely-learned man and a proponent of Korean self-consciou-seness like his fellow Pragmafist against then prevailing Chinese influence, which had already penetrated deeply into ordinary life style. According to this fact we can see not only the general dress-cystoms but the new customs of some high-birth People with evident self-consciouseness like him at that time. For example, they wore "Sim Eui" and "Bok Gun" as the dress of their ordinary life in spite of the general dress custom wearing the "Do Po" (Traditional Korean full-dress attire) and "Gat" (Traditional cylindrical Korean hat) as an ordinary or a ceremonial dress irrespective of rank at that time. Women wore an overcoat with "Chima" and "Jur. Go Ri" instead of the shortened "Jur, Go Ri" and buttock exagerating "Chima" largely popular at that time too. And also wore "So Eui" instead of "won Sam" or "Dang Eui" prevailing for the psychological resemblance of higher ranking group. Male yougnsters wore "Sa Gyu Sam" as an ordinary life dress and Girls wore "Chima and Jur Go Ri".