• Journal of Electrical Engineering and Technology
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• 제13권1호
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• pp.201-210
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• 2018

This paper proposes a new start-up method for a load commutated inverter (LCI) in a large synchronous gas-turbine generator. The initial rotor position for start-up torque is detected by the proposed initial angle detector, which consists of an integrator and a phase-locked loop. The initial rotor position is accurately detected within 150ms, and the angle difference between the real position and the detected position is less than 1%. The LCI system operates in two modes (forced commutation mode and natural commutation mode) according to operating speed range. The proposed controllers include a forced commutation controller for the low-speed range, a PI speed controller and a PI current controller, where the forced commutation controller is connected to the current controller in parallel. The current controller is modeled by Matlab/Simulink, where a six-pulse delay of the thyristor and a processing delay are considered by using a zero-order hold. The performance of the proposed start-up method is evaluated in Matlab/Psim at standstill and at low speed. To verify the feasibility of the method, a 5kVA LCI system prototype is implemented, and the proposed initial angle detector and the system performance are confirmed by experimental results from standstill to 900rpm.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2005년도 하계학술대회
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• pp.159-165
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• 2005

The proposed optical transmitter is composed of FF(flip flop) , PLL (phase locked loop), reference clock generator, serializer and LD driver 10x250 Mb/s data arrays are translated to the 2.5 Gb/s data signal by serializer. In this case, 1 data bus is allocated usually as a reference clock for synchronization. In this proposed optical transmitter, 125 MHz reference clock is generated from 10x250 Mb/s data arrays by reference clock generator. From this method. absent of reference clock bus is available and more data transmission become possible. To achieve high speed operation, the serializer circuit is designed as two stacks. For 10:1 serialization, 10 clocks that have 1/10 lambda differences is essential, so the VCO (voltage controlled oscillator) composed of 10 delay buffers is designed. PLL is for runing at 250 MHz, and dual PFD(phase frequency detector) is adopted for fast locking time. The optical transmitter is designed by using 0.35 um CMOS technology.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 하계학술대회 논문집 B
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• pp.1477-1479
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• 2004

Increasing numbers of photovoltaic arrays are being connected to the power utility through the power conditioning systems (PCS). This has raised potential problems of network protection. If, due to the action of the PCS, the local network voltage and frequency remain within regulatory limits when the utility is disconnected, then islanding is said to occur. In this paper, the representative methods to prevent the islanding are described and a PSIM-based model and analysis of the reactive power variation (RPV) method are presented. A novel phase detector using the all-pass filter and digital phase locked loop (DPLL) is proposed especially for the single-phase PCS. Finally, this paper provides the simulation and experimental results with a single-phase 3kW prototype PCS. Islanding test method of IEEE Std. 929-2000 was performed for verification.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제54권12호
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• pp.609-615
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• 2005

A 30kW electrical power conversion system is developed for a variable speed wind turbine. In the wind energy conversion system(WECS) a synchronous generator with field current excitation converts the mechanical energy into electrical energy. As the voltage and the frequency of the generator output vary according to the wind speed, a 6-bridge diode rectifier and a PWM boost chopper is utilized as an ac-dc converter maintaining the constant dc-link voltage with only single switch control. An input current control algorithm for maximum power generation during the variable speed operation is proposed without any usage of speed sensor. Grid connection type PWM inverter converts dc input power to ac output currents into the grid. The active power to the grid is controlled by q-axis current and the reactive power is controlled by d-axis current with appropriate decoupling. The phase angle of utility voltage is detected using software PLL(Phased Locked Loop) in d-q synchronous reference frame. Experimental results from the test of 30kW prototype wind turbine system show that the generator power can be controlled effectively during the variable speed operation without any speed sensor.

• 전력전자학회논문지
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• 제8권6호
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• pp.543-550
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• 2003

본 논문에서는 2대의 다이오드 정류기에 부스트 컨버터를 이용하여 전류의 파형을 능동적으로 만들어 정현파의 입력전류를 얻는 새로운 방식의 고조파 저감방식을 제안한다. 제안한 방식으로 고역률의 전원 품질을 얻을 수 있으며 입력측의 변동에 대한 출력전압의 조정도 가능하다. 또한 저감된 용량을 갖는 3상 오토트랜스포머의 사용으로 기존의 $\Delta$-Y 변압기에 비해 KVA정격이 75% 절감되며 상간변압기도 필요 없다. 본 방식을 소형화와 고품질의 전원이 요구되는 통신용 정류기등에 적용하면 효과적이다. 제안한 방식의 동작원리, 제어 및 설계방법을 기술하고 1.5KW급 시작품으로부터의 실험결과를 제시한다.

• Journal of Power Electronics
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• 제18권6호
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• pp.1830-1843
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• 2018

In this paper, the generation of a reference current and voltage signal based on a Kalman filter is offered for a 3-phase 4wire UPQC (Unified Power Quality Conditioner). The performance of the UPQC is improved with source voltages that are distorted due to harmonic components. Despite harmonic and frequency variations, the Kalman filter is capable enough to determine the amplitude and the phase angle of load currents and source voltages. The calculation of the first state is sufficient to identify the fundamental components of the current, voltage and angle. Therefore, the Kalman state estimator is fast and simple. A Kalman based control strategy is proposed and implemented for a UPQC in a distribution system. The performance of the proposed control strategy is assessed for all possible source conditions with varying nonlinear and linear loads. The functioning of the proposed control algorithm with a UPQC is scrutinized and validated through simulations employing MATLAB/Simulink software. Using a FPGA SPATRAN 3A DSP board, the proposed algorithm is developed and implemented. A small-scale laboratory prototype is built to verify the simulation results. The stated control scheme for the UPQC reduces the following issues, voltage sags, voltage swells, harmonic distortions (voltage and current), unbalanced supply voltage and unbalanced power factor under dynamic and steady-state operating conditions.

• 대한전자공학회논문지
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• 제21권3호
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• pp.6-12
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• 1984

기존의 2단 양자화된 1차 디지탈 위상포착회로(DPLL)의 포착시간과 정상상태에서의 위상오차를 줄이기 위한 방법을 연구하였다. 기본적인 DPLL에 하향(falling) 영전위교차시간을 검출하여 위상을 교정하는 회로를 첨가하여 그 성능을 개선하기 위한 연구를 하였으며 기본적인 DPLL의 성능과 비교하였다. 그래프방식을 사용하여 잡음이 없는 상태에서 위상스텝 및 주파수 스텝입력에 대한 DPLL의 위상포착과정을 시각적으로 해석하였다. 정현파 입력에 협대역임의잡음(narrow band random noise)이 섞여 있을 때 DPLL의 성능을 분석하기 위해서 Chapman-Kolmogorov 방정식을 사용하였다. 이 방법은 컴퓨터에 의한 모의 시험을 통하여 입증되었다. 수정된 DPLL의 정상상태의 위상오차와 평균포착시간이 기본적인 DPLL의 그것들과 비교되었다. 수정된 DPLL의 포착시간은 거의 두 배 정도 빨라졌으며 정상상태의 위상오차는 신호대잡음비가 커짐에 따라 개선의 폭이 중가하여 결국 영에 접근함을 알 수 있었다.

• 한국산업정보학회논문지
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• 제19권4호
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• pp.17-24
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• 2014

본 논문에서 2개의 다른 특성을 갖는 FM 안테나들을 사용할 수 있도록 자동 변환 매칭 네트워크를 갖는 CMOS FM 수신기 프론트엔드 구조를 제안하였고 이를 65nm CMOS 공정을 이용하여 설계하였다. 제안된 FM 수신기는 높은 주파수 선택 특성을 갖는 임베디드 안테나를 사용 시 FM 전체 주파수 밴드에서 일정한 수신감도를 유지하기 위해서 저 잡음 증폭기의 입력 매칭 회로의 공진 주파수를 채널 주파수에 따라 가변이 가능하도록 구현하였다. 구현된 FM 프론트엔드의 시뮬레이션 결과는 약 38dB 전압이득, 2.5dB 이하의 잡음 지수 특성, -15.5dBm의 IIP3 선형성 특성을 보이고 1.8V 전원에 3.5mA 전류를 소모한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.272-281
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• 2013

This paper presents low power frequency shift keying (FSK) transmitter using all digital PLL (ADPLL) for smart utility network (SUN). In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The FSK transmitter is implemented in $0.18{\mu}m$ 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is $3.5mm^2$. The power consumption of the ADPLL is 12.43 mW. And, the power consumptions of the transmitter are 35.36 mW and 65.57 mW when the output power levels are -1.6 dBm and +12 dBm, respectively. Both of them are supplied by 1.8 V voltage source. The frequency resolution of the TDC is 2.7 ps. The effective DCO frequency resolution with the differential MOS varactor and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.8 GHz is -121.17 dBc/Hz with a 1 MHz offset.

• 한국인터넷방송통신학회논문지
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• 제12권5호
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• pp.1-9
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• 2012

본 논문은 레이더 시스템에 적용되는 고성능 PLL 주파수 합성기를 설계하고, 그 성능을 분석하였다. 소형화제작을 위해 PLL 간접합성방식을 적용하였으며, 광대역특성에서 우수한 위상잡음과 고속의 주파수합성시간을 갖기 위해 offset 방식의 PLL에 DDS를 기준신호로 설계 하였다. 또한, offset PLL에서 고속의 주파수 변환을 위해 DAC를 이용하여 coarse tune을 적용하였다. 이러한 구조에서의 성능 예측을 위해 각각의 잡음원에 대해 모델링을 적용하여 출력위상잡음을 예측하였으며, 제작결과와 비교 분석하였다. 그 결과 simulation과 측정결과가 일치함을 확인하였으며, 100KHz 옵셋 주파수에서 -126dBc/Hz의 우수한 위상잡음 특성과 10usec 이내의 고속의 주파수변환시간을 갖는 항공기용 레이더 주파수합성기를 설계하였다.