• Journal of the Korean Society for Precision Engineering
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• v.4 no.4
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• pp.25-35
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• 1987

This paper deals with the design of the digital controller for DC servo motor, and it is implemented for the cartesian coordinate 4 axes manipulator. A design method of the controller is adopted an algorithm using the digital position locked loop(DPLL) method and the linear PID control for the smooth motion. To simplify the hardware configuration of control system, 8279 keyboard/display controller, Z-80 CTC counter and 8255 PPI are used. Therefore the design method to control each motor as real-time is presented. To show effectiveness of the design, the PWM circuit and frequency/voltage converter are applied for the velocity control of robot system. When the proposed controller is applied to the 4-axes manipulator, it reveals that the error probabilities of X, Y and Z axis as 0.033%, 0.023% and 0.028% respectively.

• Journal of the Korea Institute of Military Science and Technology
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• v.9 no.3
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• pp.116-122
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• 2006

A fast scan digital-IF FFT receiver at the radio communication band is presented for spectrum monitoring applications. It is composed of three parts: RF front-end, fast LO board, and signal processing board. It has about 19GHz/s scan rate, multi frequency resolution from 10kHz to 2.5kHz, and high sensitivity of below -99dBm. The design and performance analysis of the digital-IF FFT receiver are presented.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.778-782
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• 2004

본 논문에서는 전력 품질 기기의 제어에 있어서 필수적 요소라고 할 수 있는 전원각을 찾는 방법중에서 PLL(Phase Locked Loop)에 관하여 기존의 방식들을 먼저 알아보고, 정상분을 추출하여 이용하는 기존의 PLL 방식을 무정전전원장치에 적합한 형태로 개선한 주파수를 제한한 PLL 방식을 제안하였다. 제안된 PLL 방식은 기존의 PI 제어기에 주파수 제한기(limiter)와 안티 와인드업(anti-windup)을 추가하였다. 이것의 기본적인 동작 원리는 기존의 방법들과 같지만, 차이점은 주파수 제한기의 삽입으로 인하여 주파수 변동률을 일정한 범위 내에서 제한할 수 있다는 것이다. 기존의 PLL 방법과 본 논문에서 제안된 주파수를 제한한 PLL 방법의 차이를 알아보기 위하여 동적 전압 보상기로 전압을 보상하는 시뮬레이션을 하였고, 결과적으로 제안된 주파수를 제한한 PLL 방법이 기존의 PLL 방법보다 UPS에 적합함을 입증하였다.

• Journal of Positioning, Navigation, and Timing
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• v.6 no.4
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• pp.135-140
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• 2017

This paper proposes a signal merging algorithm to increase the signal-to-noise ratio (SNR) of a GPS correlator output to estimate the roll angle of a rotating vehicle in a weak GPS signal environment. Rotation Locked Loop (RLL) algorithm is used to estimate a roll angle using the characteristics that the power of the GPS signal measured at the receiver of a rotating vehicle varies periodically. First, delay times are calculated to synchronize GPS signals using satellites' and receiver's positions and the rotation frequency of a vehicle, and then correlator outputs are delayed in time and merged with each other, resulting in the increase of an SNR in a correlator output. Finally, simulations are conducted and the performance of the proposed algorithm is validated.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.11 no.3
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• pp.211-216
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• 1986

This paper presents theoretical analysis and experimental results on an improved interference rejection circuit in the presence of continuous wave interference at center frequency, particularly in a wide-band communication systems. This circuit is based upon a phase locked loop for estimating the CW interference phase and the MSE technique to minimize the estimation error. Therefore, the introduced rejection circuit that minimized the estimated phase error outperforms the rejection circuit with phase estimation only. As a result of experiment, we confirm that this proposed rejection circuit gives a high degree of interference rejection performances when the input J/S is large.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.394-397
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• 2002

A design study of phase detectors for the 2.5 Gb/s CDR circuit using a standard 0.18-${\mu}{\textrm}{m}$ CMOS process has been performed. The targeted CDR is based on the phase-locked loop and thus it consists of a phase detector, a charge pump, a LPF, and a VCO. For high frequency operation of 2.5 Gb/s, phase detector and charge pump, which accurately compare phase errors to reduce clock jitter, are critical for designing a reliable CDR circuit. As a phase detector, the Hogge phase detector is selected but two transistors are added to improve the performance of the D-F/F. The charge pump was also designed to be placed indirectly input and output.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.340-343
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• 1999

In this paper, we propose a wide range PLL(Phase Locked Loop) for 64X CD-ROMs & l0X DVD-ROMs. The frequency locking range of the Proposed PLL is 75MHz~370MHz. To reduce jitters caused by large VCO gain and supply voltage noise, a new V-I converter and a differential delay cell are used in 3-stage ring VCO, respectively. The new V-I converter has a 0.6V ~ 2.5V wide input range. In addition, we propose a new charge pump which has perfect current matching characteristics for the sourcing/sinking current. This new charge pump improves the locking time and the locking range of the PLL. This Chip is implemented in 0.25${\mu}{\textrm}{m}$ CMOS process. It consumes 55㎽ in worst case with a single 2.5V power supply.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2180-2183
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• 2003

본 논문에서는 광 디스크의 기록 밀도 증가에 따른 신호품질의 열화나 노이즈가 심한 환경에서 DPLL(Digital Phase Locked Loop)의 성능을 개선하기 위한 FD(Frequency Detector)와 PD(Phase Detector) 알고리즘을 제안한다. 제안된 PD 알고리즘은 노이즈에 의해 왜곡되어 RLL 조건을 위배하는 입력신호, 즉 RLL 조건에 의해 결정되는 최소 런 길이보다 주기가 작은 신호에 의해 발생하는 위상오차를 위상오차 보정 시 사용하지 않도록 설계하여 잘못된 정보에 의한 위상오차 보정이 일어나지 않도록 하였다 제안된 FD 알고리즘은 주파수를 추적하기 위해 삽입되는 신호인 Sync 신호의 symmetry 특성을 이용하여 샘플패턴을 검출하도록 하여 기존의 주파수 오차 보정 알고리즘보다 향상된 주파수 추적 성능을 가지도록 하였다.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.649-659
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• 2003

OFDM/FH communication system Is widely used in the wireless communication for the large capacity and high-speed data transmission. However, phase noise and PAPR (peak-to-average power ratio) are the serious problems causing performance impairment. In this paper, PLL (phase locked loop) frequency synthesizer with high switching speed is used for the phase noise model. SSPA and TWTA are considered for the nonlinear HPA model. Under these conditions and by approximating $e^{j{\phi}[m]}$ into $1 + j{\phi}[m]-\frac{1}{2}{\phi}^2[m]$ for the phase noise nonlinear approximation, SINR (signal-to-interference-noise-ratio) with nonlinear HPA and phase noise is derived in the OFDM/FH system. The bit error probabilities (BER) are found by computer simulation method and semi-analytical method. The simulation results closely match with the semi-analytical results.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.1018-1023
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• 1998

This paper presents an effective control scheme incorporated in the voltage-fed half-bridge series resonant inverter for induction heating applications, which is based upon a load-adaptive tuned frequency tracking control strategy using PLL(Phase Locked Loop) and its peripheral control circuit. The proposed control strategy ensures a stable operation characteristics of overall inverter system and ZVS(Zero Voltage Switching0 operation in spite of sensitive load parameters variation as well as power regulation, specially in the non-magnetic heating loads. The simulation results and the performance characteristics in the steady-state are shown as compared with the experimental results for a prototype induction cooking system rated at 1.2kW.