• Transactions on Electrical and Electronic Materials
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• 제2권4호
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• pp.1-6
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• 2001

In this paper, a 1.5 V high-gain high-frequency CMOS complementary operational amplifier is presented. The input stage of op-amp is designed for supporting the constant transconductance on the Input stage by consisting of the parallel-connected rail-to-rail complementary differential pairs. And consisting of the class-AB rail-to-rail output stage using the concept of elementary shunt stage and the grounded-gate cascode compensation technique for improving the low PSRR which was a disadvantage in the general CMOS complementary input stage, the load dependence of open loop gain and the stability of op- amp on the output load are improved, and the high-gain high-frequency operation can be achieved. The designed op-amp operates perfectly on the complementary mode with the 180° phase conversion for a 1.5 V supply voltage, and shows the DC open loop gain of 84 dB, the phase margin of 65°, and the unity gain frequency of 20 MHz. In addition, the amplifier shows the 0.1 % settling time of .179 ㎲ for the positive step and 0.154 ㎲ for the negative step on the 100 mV small-signal step, respectively, and shows the total power dissipation of 8.93 mW.

• 한국산학기술학회:학술대회논문집
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• 한국산학기술학회 2006년도 춘계학술발표논문집
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• pp.348-351
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• 2006

This paper proposes a modified IMC-PID controller that introduces controlling factor of the system identification to the standard IMC-PID controller in order to meet the design specifications such as gain, phase margin and maximum magnitude of sensitivity function in the frequency domain as well as the design specifications in time domain, settling, rising time and overshoot, and so on.

• IEIE Transactions on Smart Processing and Computing
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• 제4권1호
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• pp.44-50
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• 2015

This paper presents a high speed synchronous single inductor dual output boost converter using Type-III compensation for power management in smart devices. Maintaining multiple outputs from a single inductor is becoming very important because of inductor the sizes. The uses of high switching frequency, inductor and capacitor sizes are reduced. Owing to synchronous rectification this kind of converter is suitable for SoC. The phase is controlled in time sharing manner for each output. The controller used here is Type-III, which ensures quick settling time and high stability. The outputs are stable within $58{\mu}s$. The simulation results show that the proposed scheme achieves a better overall performance. The input voltage is 1.8V, switching frequency is 5MHz, and the inductor used is 600nH. The output voltages and powers are 2.6V& 3.3V and 147mW &, 230mW respectively.

• Journal of electromagnetic engineering and science
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• 제7권4호
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• pp.161-168
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• 2007

A fast correlative vector direction finding(CVDF) system using active dipole antenna array for mobile direction finding(DF) applications is presented. To develop the CVDF system, the main elements such as active dipole antenna, multi-channel direction finder, and search receiver are designed and analyzed. The active antenna is designed as composite structure to improve the filed strength sensitivity over the wide frequency range, and the multi-channel direction finder and search receiver are designed using DDS-based PLL with settling time of below 35 us to achieve short signal processing time. This system provides the capabilities of the high DF sensitivity over the wide frequency range and allows for high probability of intercept and accurate angle of arrival(AOA) estimation for agile signals. The design and performance analysis according to the external noise and modulation schemes of the CVDF system with five-element circular array are presented in detail.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권4호
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• pp.506-517
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• 2015

This paper presents a 1.248 Gb/s - 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is $0.01{\mu}s$ the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a $0.11{\mu}m$ CMOS process, and the die area is $600{\mu}m{\times}250{\mu}m$. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are $35.24ps_{p-p}$ and $4.25ps_{rms}$ respectively for HS-G2 mode.

• Journal of Electrical Engineering and Technology
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• 제11권6호
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• pp.1535-1547
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• 2016

This paper proposes various design procedures for computing Power System Ancillary Service Requirement Assessment Indices (PSASRAI) for a Two-Area Thermal Reheat Interconnected Power System (TATRIPS) in a restructured environment. In an interconnected power system, a sudden load perturbation in any area causes the deviation of frequencies of all the areas and also in the tie-line powers. This has to be corrected to ensure the generation and distribution of electric power companies to ensure good quality. A simple Proportional and Integral (PI) controllers have wide usages in controlling the Load Frequency Control (LFC) problems. So the design of the PI controller gains for the restructured power system are obtained using Bacterial Foraging Optimization (BFO) algorithm. From the simulation results, the PSASRAI are calculated based on the settling time and peak over shoot concept of control input deviations of each area for different possible transactions. These Indices are useful for system operator to prepare the power system restoration plans. Moreover, the LFC loop coordinated with Redox Flow Batteries (RFB) has greatly improved the dynamic response and it reduces the control input requirements and to ensure improved PSASRAI, thereby improving the system reliability.

• 한국지능시스템학회논문지
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• 제7권2호
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• pp.52-65
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• 1997

이 논문은 전력계통의 부하주파수 제어를 위한 자기조정 퍼지제어기의 설계기법을 제시한다. 제안된 퍼지제어기의 파라미터 자기조정 알고리즘은 퍼지제어기의 추론값과 최적 제어기의 출력값들 사이의 오차를 감소시키는 네개의 방향 벡터를 사용하는 구배법에 기초를 둔다. 최적 제어기로부터 얻어진 입,출력 데이터쌍을 사용하여, 퍼지추론 룰의 전건부와 후건부에서의 파라미터들은 제안된 구배법에 으해 자동조정되고 학습되어진다. 시뮬레이션 결과, 제안된 퍼지제어기가 종래의 제어기보다 우수한 제어성능을 보임을 확인하였다.

• 한국콘텐츠학회논문지
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• 제18권10호
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• pp.478-489
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• 2018

본 연구에서는 사용자의 현재와 기대 스크립트를 기반으로 커피 전문점의 서비스디자인을 위한 규준 스크립트를 설계하였다. 1) 현재와 기대 스크립트에 포함된 활동들을 확인하였다. 2) 현재와 기대 스크립트에서 고빈도의 활동들을 선정하였다. 그런 후 이 둘을 통합하여 장면별로 분류하였다. 3) 통합된 장면과 활동들에 대한 중요도를 평가하였다. 4) 일정한 규칙에 따라 불필요한 활동들을 삭제하거나 선택 항목으로 제외하였다. 그리고 나머지 활동들을 장면별로 분류하고 순서대로 나열하여 하나의 규준 스크립트를 완성하였다. 각 장면에 속한 활동들 하나하나가 서비스 접점이 되었다. 장면은 '들어가기', '자리 정하기', '주문하기', '음료 기다리기', '음료 받기', '음료를 마시며 시간 보내기', '화장실 가기', 그리고 '나가기'로 구성되었다. '들어가기'에는 2개, '자리 정하기'에는 6개, '주문하기'에는 11개, '음료 기다리기'에는 2개, '음료 받기'에는 4개, '음료를 마시며 시간 보내기'에는 6개, '화장실 가기'에는 3개, 그리고 '나가기'에는 4개의 활동들이 포함되었다. 이러한 결과들과 함께 특이점을 논의하였으며, 마지막에는 연구의 의의와 제한점을 추가하였다.

• 한국전자파학회논문지
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• 제15권12호
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• pp.1161-1167
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• 2004

기존의 PLL(phase locked loop)은 폐루프 구조이므로 주파수 스위칭 속도가 낮은 단점을 갖는다. 이를 개선하기 위해서 개루프 구조를 혼합한 Digital Hybrid PLL 구조를 연구하였다. 또한 이 구조는 빠른 주파수 스위칭 속도로 동작할 수 있지만, VCO의 전압대 주파수 전달특성을 ROM 형태로 구현하는 DLT(digital look-up table)이 사용되어야 하므로 회로소자가 많아지고 소비전력이 증가된다. 그러므로, 본 논문에서는 복잡한 DLT의 구조를 간단한 Digital logic 회로로 대체시킨 새로운 구조를 제안하였다. 또한 주파수 합성때마다 타이밍 동기화를 이루는 회로를 설계하여 합성기의 항상성을 확보하였으며 DLT를 사용하는 방식과 비교하여 회로소자를 약 $28\%$정도 줄일 수 있다. 고속 스위칭 동작 특성과 주파수 합성을 시뮬레이션과 실제 회로 구현으로 확인하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 학술대회 논문집 정보 및 제어부문
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• pp.158-160
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• 2005

This paper presents a new approach to the problem of designing a cascaded three-parameters controller for a given linear time invariant (LTD plant in unity feedback system. We consider a proportional-integral-derivative (PID) and a first-order controller with specified overshoot and settling time. This problem is difficult to solve because there may be no analytical solution due to the use of low-order controller and furthermore. the zeros of controller just appear in the zeros of feedback system. The key idea of our method is to impose a constraint on the controller parameters so that the zeros of resulting controller are distant from the dominant pole of closed-loop system to the left as far as the given interval. Two methods realizing the idea are suggested. We have employed the characteristic ratio assignment (CRA) in order to deal with the time response specifications. It is noted that the proposed methods are accomplished only in parameter space. Several illustrative examples are given.