• Proceedings of the KIEE Conference
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• 2004.10a
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• pp.224-226
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• 2004

Digital Kalman filter is presented as a powerful approach to obtain the reference estimation of the control current for shunt active power filter. This algorithm provides the best estimate of the fundamental and harmonic frequency components from the sampled values of the line current or voltage. By adopting of the digital Kalman filtering algorithm, the structure of the control algorithm eliminates the need of a Phase locked loop(PLL) for the synchronization of the reference signal used in the compensation and it not sensitive to the distortion of the line voltage. The effectiveness of the algorithm is confirmed by the computer simulations.

• Proceedings of the KSR Conference
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• 2004.10a
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• pp.1480-1485
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• 2004

In this paper, a real-time digital kalman filtering algorithm is used to obtain the reference estimation of the control current for shunt active power filter. This algorithm provides the best estimate of the fundamental and harmonic frequency components from the sampled values of the line current or voltage waveform. By adopting of the digital Kalman filtering algorithm, the structure of the control algorithm eliminates the need of a Phase locked loop(PLL) for the synchronization of the reference signal used in the compensation and it not sensitive to the distortion of the line voltage. The effectiveness of the algorithm is confirmed by the computer simulations.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.605-606
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• 2006

Voltage Controlled Oscillator(VCO) plays an important role in today's communication systems. Especially, a Clock Generator(CG) in phase-locked loop(PLL) is usually realized by the VCO. This paper proposes a new VCO with a controllable duty cycle buffer, that can be adopted in low-power high-speed communication systems. Delay cell of the VCO is implemented with gilbert cell. Frequency dynamic range of the VCO is in the range of approximately $50MHz{\sim}500MHz$. Parameters with N-well CMOS 0.18-um process with 1.8V supply voltage was used for the simulations.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.5
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• pp.13-18
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• 1978

A delay switching PLL (DSPLL) is proposed for improvement of the frequency acquisition Performance (pull-in range) while keeping a narrow bandwidth LPF. It has, between the phase detector and the LPF, just a simple RC delay circuit, a switch and another phase detector controlling the switching time. For the common second order PLL, the pull-in capability of the DSPLL is analyzed approximately, without considering additive white noise effect, and verified experimentally. It is shown that the delay switching extends the pull-in range significantly, as much as a half of lock-range. At the phase tracking mode, the delay switching does not function, to make the DSPLL be a normal PLL.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.145-151
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• 2013

In this paper, a low power, small area cyclic time-to-digital converter in All-Digital PLL for DVB-S2 application is presented. Coarse and fine TDC stages in the two-step TDC are shared to reduce the area and the current consumption maintaining the resolution since the area of the TDC is dominant in the ADPLL. It is implemented in a 0.13 ${\mu}m$ CMOS process with a die area of 0.12 $mm^2$. The power consumption is 2.4 mW at a 1.2 V supply voltage. Furthermore, the resolution and input frequency of the TDC are 5 ps and 25 MHz, respectively.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.8
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• pp.417-425
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• 1999

This paper presents an effective control scheme with the voltage-fed half-bridge series resonant inverter for induction heating system, which is based upon a load-adaptive tuned frequency tracking control strategy using PLL(Phase Locked Loop) and its peripheral control circuits. The proposed control strategy ensures a stable operation characteristics of overall inverter system and ZVS(Zero Voltage Switching) irrespective of sensitive load parameter variations, specially in the non-magnetic materials as well as power regulation. The detail operation principle and the characteristics of inverter system with the proposed control scheme are described and its validity is verified by the simulation and the experimental results for a prototype induction cooking system rated at 1.2kW.

• Journal of Power Electronics
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• v.6 no.3
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• pp.195-204
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• 2006

This paper presents a new compensating system, consisting of series and shunt active filters, for mitigating voltage and current disturbances. The shunt filter is used to compensate for unbalanced and distorted load currents. The series filter comprises two inverters, used to suppress voltage disturbances and handle source currents independently. This configuration is devised to reduce the overall cost of active compensators by using low-frequency high-current switches for the latter inverter. The filters are controlled separately using a novel control strategy. Since voltages at the point of common coupling contain interharmonics, conventional methods cannot be used for extracting voltage references. Therefore, voltage references are obtained from generated sinusoidal waveforms by a phase-locked loop. Current references are detected based on rotating frame vector mapping. Simulation results are presented to verify the system.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.494-495
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• 2012

본 논문은 LVRT 제어를 위한 계통 사고 상황에서도 정확한 위상각을 검출하기 위하여 일반화된 2차 적분기(Second Order Generalized Integrator)를 이용한 정상분 전압 검출을 기반으로 하며, 주파수 변동에도 강인성 제어가 가능한 DSOGI (Double Second Order Generalized Integrator) FLL(Frequency locked loop)을 제안한다. 실험을 통해 종래의 SRF(Synchronous reference frame) PLL, DSOGI PLL 제어와 비교, 분석을 통해 본 논문의 타당성을 입증한다.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.107-113
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• 2014

A VCO (Voltage Controlled Oscillator) and a divide-by-4 high speed frequency divider are implemented using 65nm CMOS technology for 60GHz wireless communication system. The mm-wave VCO was designed by NMOS cross-coupled LC type using current source. The architecture of the divide-by-4 high speed frequency divider is differential ILFD (Injection Locking Frequency Divider) with varactor to control frequency range. The frequency divider also uses current sources to get good phase noise characteristics. The measured results show that the VCO has 64.36~67.68GHz tuning range and the frequency divider divides the VCO output by 4 exactly. The high output power of 5.47~5.97dBm from the frequency divider is measured. The phase noise of the VCO including the frequency divider are -77.17dBc/Hz at 1MHz and -110.83dBc/Hz at 10MHz offset frequency. The power consumption including VCO is 38.4mW with 1.2V supply voltage.