• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1252-1258
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• 1999

This paper describes a COMS IF transceiver IC for 10-MHz bandwidth wireless local loops. It interfaces between the RF section and the digital MODEM section and performs the IF-to-baseband (Rx) and baseband-to-IF (Tx) frequency conversions. The chip incorporates variable gain amplifiers, phase-locked loops, low pass filters, analog-to-digital and digital-to-analog converters. It has been implemented in a 0.6 -${\mu}{\textrm}{m}$ 2-poly 3-metal CMOS process. The phase-locked loops include voltage-controlled oscillators, dividers, phase detectors, and charge pumps on chip. The only external complonents are the filter and the varactor-tuned LC tank circuit. The chip size is 4 mm $\times$ 4 mm and the total supply current is about 57 mA at 3.3 V.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.4
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• pp.117-122
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• 2018

A large-capacity three-phase system air conditioner recently includes an inverter circuit to reduce power consumption. The inverter circuit uses a DC voltage that comes from DC-link power capacitor with the function of rectifying, which means AC voltage to DC voltage using a diode. An electrolytic capacitor is generally used to satisfy the voltage ripple and current ripple conditions of a DC-link power capacitor used for rectifying. Reducing the capacitance of the capacitor decreases the size, weight, and cost of the circuit. This paper proposes an algorithm to reduce the input ripple current by combining the minimum point estimation phase locked loop (PLL) phase control and the average voltage d axis current control technique. When this algorithm was used, the input ripple current decreased by almost 90%. The current ripple of the DC-link capacitor decreased due to the decrease in input ripple current. The capacitor capacity can be reduced but the electrolytic capacitor has a heat generation problem and life-time limitations because of its large equivalent series resistance (ESR). This paper proposes a method to select a film capacitor considering the current ripple at DC-link stage instead of an electrolytic capacitor. The capacitance was selected considering the voltage limitation, RMS (Root Mean Square) current capacity, and RMS current frequency analysis. A $1680{\mu}F$ electrolytic capacitor can be reduced to a $20{\mu}F$ film capacitor, which has the benefit of size, weight and cost. These results were verified by motor operation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.13-22
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• 2001

This paper presents three dimensional structure of RF packages and the improvement effect of its electrical characteristics when implementing RF transceivers. We divided RF modules into several subunits following each subunit function based on the partitioning algorithm which suggests a method of three dimension stacking interconnection, PAA(pad area array) interconnection and stacking of three dimensional RF package structures. 224MHz ITS(Intelligent Transportation System) RF module subdivided into subunits of functional blocks of a receiver(RX), a transmitter(TX), a phase locked loop(PLL) and power(PWR) unit, simultaneously meeting the requirements of impedance characteristic and system stability. Each sub­functional unit has its own frequency region of 224MHz, 21.4MHz, and 450KHz~DC. The signal gain of receiver and transmitter unit showed 18.9㏈, 23.9㏈. PLL and PWR modules also provided stable phase locking, constant voltages which agree with design specifications and maximize their characteristics. The RF module of three dimension stacking structure showed $48cm^3$, 76.9％ reduction in volume and 4.8cm, 28.4％ in net length, 41.8$^{\circ}C$, 37% in maximum operating temperature, respectively. We have found that three dimensional PAA package structure is able to produce high speed, high density, low power characteristics and to improve its functional characteristics by subdividing RF modules according to the subunit function and the operating frequency, and the features of physical volume, electrical characteristics, and thermal conditions compared to two dimensional RF circuit modules.

• Journal of the Korean Solar Energy Society
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• v.28 no.2
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• pp.64-69
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• 2008

As the grid-connected photovoltaic power conditioning systems (PVPCS) are installed in many residential areas, these have raised potential problems of network protection on electrical power system. One of the numerous problems is an Islanding phenomenon. There has been an argument that it may be a non-issue in practice because the probability of islanding is extremely low. However, there are three counter-arguments: First, the low probability of islanding is based on the assumption of 100% power matching between the PVPCS and the islanded local loads. In fact, an islanding can be easily formed even without 100% power matching (the power mismatch could be up to 30% if only traditional protections are used, e.g. under/over voltage/frequency). The 30% power-mismatch condition will drastically increase the islanding probability. Second, even with a larger power mismatch, the time for voltage or frequency to deviate sufficiently to cause a trip, plus the time required to execute a trip (particularly if conventional switchgear is required to operate), can easily be greater than the typical re-close time on the distribution circuit. Third, the low-probability argument is based on the study of PVPCS. Especially, if the output power of PVPCS equals to power consumption of local loads, it is very difficult for the PVPCS to sustain the voltage and frequency in an islanding. Unintentional islanding of PVPCS may result in power-quality issues, interference to grid-protection devices, equipment damage, and even personnel safety hazards. Therefore the verification of anti-islanding performance is strongly needed. In this paper, improved RPV method is proposed through considering power quality and anti-islanding capacity of grid-connected single-phase PVPCS in IEEE Std 1547 ("Standard for Interconnecting Distributed Resources to Electric Power Systems"). And the simulation results are verified.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.4 s.334
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• pp.1-6
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• 2005

For the low power and low cost transceivers, direct sequence spread spec01m frequency-shift keying (DSSS-FSK) is proposed. A transmitter of the DSSS-FSK signal can be implemented by a simple direct modulation using the phase locked loop. Since the DSSS-FSK signal has negligible power around the carrier frequency, low cost direct conversion receiver can be used. Optimum coherent and semi-coherent correlation detection methods for the DSSS-FSK signal are proposed and analyzed. Segmented semi-coherent correlation detection method is proposed to improve the bit error rate performance in the large carrier frequency offset.

• Journal of Power Electronics
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• v.17 no.5
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• pp.1150-1159
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• 2017

Flexibility in the power control of ultrasonic transducers has remained a challenge for cleaning applications. This paper introduces a modification of the existing piezoelectric ceramic transducer (PCT) circuit to increase the range of operation through its impedance characteristics. The output power is controlled using the asymmetrical voltage-cancellation (AVC) method. Together with a phase-locked loop control, the switching frequency of the inverter is automatically adjusted to maintain a lagging phase angle under load-parameter variations during the cleaning process. With the proposed modification, the region of the zero-voltage switching (ZVS) operation is extended, which results in a wider range of output power control. A hardware prototype is constructed and the control algorithm is implemented using an STM32F4 microcontroller. Simulation and experimental results are provided to verify the proposed method for a 50-W PCT. The operating frequency and output power ranges under study are 37 - 41 kHz and 15.8 - 50 W, respectively.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3181-3183
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• 2000

As the fact that the simple data of text and sound in early year have been changed to be high quality images and sounds. PLL(Phase-Locked Loop) system plays an important role in communication system. VCO(Voltage Controlled Oscillator) is the most important part in PLL system because it can have critical effects on operation of PLL. Recently, it has been raised the necessity of high speed and high accuracy circuit application. In this paper, a new differential voltage clamped VCO using negative-skewed path is suggested. Using a dual-delay scheme to implement the VCO, higher operation frequency and wider tuning are achieved simultaneously. The dual-delay scheme means that both the negative skewed delay paths and the normal delay paths exist in the same ring oscillator. The negative skewed delay paths decrease the unit delay time of the ring oscillator below the single inverter delay time. As a result, higher operation frequency can be obtained. The whole characteristics of VCO are simulated by using HSPICE. Simulation results show that the resulting operating frequencies are 50% higher than those obtainable from the conventional approaches.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1684-1686
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• 2005

As photovoltaic(PV) power generation systems become more common, it will be necessary to investigate islanding detection method for PV systems. Islanding of PV systems can cause a variety of problems and must be prevented. However, if the real and reactive power of load and PV system are closely matched, islanding detection by passive methods becomes difficult. Also, most active methods lose effectiveness when there are several PV systems feeding the same island. The active frequency drift positive feedback method(AFDPF) enables islanding detection by forcing the frequency of the voltage in the island to drift up or down. In this paper the research for the minimum value of chopping fraction gain applied digital phase-locked-loop(DPLL) to AFDPF considering output power quality and islanding prevention performance are performed by simulation and experiment in IEEE Std 929-2000 islanding test.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.4
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• pp.793-796
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• 2010

The equalizer compensates a signal distorted by transmission lines and amplifying stages, so the signal can have uniform characteristics over all frequency range. The equalizer in ODD(Optical Disc Drive) improves the stability of the extracted clock from a received signal and the readability of an inserted disc by suppressing noise and ISI(Inter-Symbol Inference). The length of marks-spaces and track pitch on discs becomes shorter as the recording density of an optical media is higher, which causes noise and ISI. And, the sensitivity about the fluctuation of physical systems is higher as the optical devices become more complicate. This paper proposes a method to select the coefficient of built-in equalizer of ODD in order to maintain the quality of signals against noise and ISI caused by system fluctuation.

• Proceedings of the Optical Society of Korea Conference
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• 2002.07a
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• pp.68-69
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• 2002

두 대의 결맞은 레이저는 원자의 고분해 분광이나 광통신 등의 여러 분야에서 응용이 가능하다. 본 연구에서는 세슘 원자분수 주파수표준기와 저속 원자빔 주파수표준기에서 원자의 속도 선택 실험에 사용하기 위한 9.2 GHz의 주파수 차이를 가지는 두 대의 결맞은 레이저를 제작하였다. 결맞은 레이저는 주입 잠금(injection locking)이나 위상 잠금 회로(phase locking loop)를 이용하여 만들 수 있다. (중략)