• Journal of Power Electronics
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• v.12 no.6
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• pp.851-858
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• 2012

This paper presents resonant inverter tuning for current source parallel resonant induction heating systems based on a new self oscillating switching technique. The phase error is suppressed in a wide range of operating frequencies in comparison with Phase Locked Loop (PLL) techniques. The proposed switching method has the capability of tuning under fast changes in the resonant frequency. According to this switching method, a multi-frequency induction heating (IH) system is proposed by using a single inverter. In comparison with multi-level inverter based IH systems, the advantages of this technique are its simple structure, better transients and wide range of operating frequencies. A laboratory prototype was built with an operating frequency of 35 kHz to 55 kHz and 300 W of output power. The performance of the IH system shows the validity of the new switching technique.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1711-1712
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• 2007

액체탱크의 레벨을 정밀측정하는 데 FMCW(Frequency Modulated Continuous Wave)를 이용하고자 한다. 우리는 1GHz 대역폭으로 Sweep하는 Frequency Source Module을 개발하여 테스트 중이다. 개발한 송수신 모듈은 주파수의 송수신을 위한 주요부품들로 구성되는데, VCO(Voltage Controlled Oscillator), 서큘레이터(Circulator), 필터(Filter), 전력분배기(Power Divider), PLL(Phase Locked Loop)제어부, 믹서, 증폭기 등이 그것이다. 이들 부품들이 위치한 RF Board와, 패치로 구성한 안테나를 이용하여 마이크로웨이브 신호를 송수신할 수 있으며, 송수신한 신호 간의 차주파수(beat frequency)성분을 측정하면 거리정보를 획득할 수 있다. 차주파수의 아날로그신호는 DSP를 이용하여 FFT를 수행하여 주파수 성분을 찾아 거리계산을 하도록 개발하였다. 거리 측정의 성능에 영향을 미치는 가장 큰 요소는 안정된 주파수를 만들어 낼 수 있느냐 하는 것이다. 본 논문에서는 제작한 VCO 모듈을 비롯한 개발 중인 각 모듈들을 소개하였다. 향후 VCO의 선형성 개선과, 난반사에 대한 Echo Cancel 알고리듬을 적용하여 제품의 상용화를 목표로 한다.

• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.6
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• pp.381-388
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• 2018

A novel and simple algorithm for accurate calculation of RMS voltage is proposed in a digitally controlled grid-tie inverter system. Given that the actual frequency of grid voltage is continuously changing, the constant sampling frequency cannot be a multiple number of the fundamental frequency. Therefore, the RMS of grid voltage contains periodic oscillations due to the differences in the phase angle of sampled data during calculation. The proposed algorithm precisely calculates and updates the initial phase angle of the first sampled voltage in a half-cycle period using phase-locked loop, which is commonly utilized for phase angle detection in grid-tie inverter systems. The accuracy and dynamic performance of the proposed algorithm are compared with those of other algorithms through various simulations and experiments.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.451-454
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• 2011

In this paper, a wideband clock generator using novel Automatic frequency calibration(AFC) scheme is proposed. Wideband clock generator using AFC has the advantage of small VCO gain and wide frequency band. The conventional AFC compares whether the feedback frequency is faster or slower then the reference frequency. However, the proposed AFC can detect frequency difference between reference frequency with feedback frequency. So it can be reduced an operation time than conventional methods AFC. Conventional AFC goes to the initial code if the frequency step changed. This AFC, on the other hand, can a prior state code so it can approach a fast operation. In simulation results, the proposed clock generator is designed for DisplayPort using the CMOS ring-VCO. The VCO tuning range is 350MHz, and a VCO frequency is 270MHz. The lock time of clock generator is less then 3us at input reference frequency, 67.5MHz. The phase noise is -109dBC/Hz at 1MHz offset from the center frequency. and power consumption is 10.1mW at 1.8V supply and layout area is $0.384mm^2$.

• Journal of Electrical Engineering and Technology
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• v.12 no.3
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• pp.1101-1107
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• 2017

In this paper, a robust and fast grid synchronization method of a three-phase power converter is proposed. The amplitude and phase information of grid voltages are essential for power converters to be properly connected into the utility. The phase-lock-loop in synchronous reference frame has been widely adopted for the three-phase converter system since it shows a satisfactory performance under balanced grid voltages. However, power converters often operate under abnormal grid conditions, i.e. unbalanced by grid faults and frequency variations, and thus a proper active and reactive power control cannot be guaranteed. The proposed method adopts a second order generalized integrator in synchronous reference frame to detect positive sequence components under unbalanced grid voltages. The proposed method has a fast and robust performance due to its higher gain and frequency adaptive capability. Simulation and experimental results show the verification of the proposed synchronization algorithm and the effectiveness to detect positive sequence voltage.

• Transactions on Electrical and Electronic Materials
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• v.15 no.6
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• pp.309-314
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• 2014

This work proposes an integrated high frequency divider with an inductive peaking technique implemented in a current mode logic (CML) frequency divider. The proposed divider is composed with a master-slave flip-flop, and the master-slave flip-flop acts as a latch and read circuits which have the differential pair and cross-coupled n-MOSFETs. The cascode bias is applied in an inductive peaking circuit as a current source and the cascode bias is used for its high current driving capability and stable frequency response. The proposed divider is designed with $0.18-{\mu}m$ CMOS process, and the simulation used to evaluate the divider is performed with phase-locked loop (PLL) circuit as a feedback circuit. A divide-by-two operation is properly performed at a high frequency of 20 GHz. In the output frequency spectrum of the PLL, a peak frequency of 2 GHz is obtained witha divide-by-eight circuit at an input frequency of 250 MHz. The reference spur is obtained at -64 dBc and the power consumption is 13 mW.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.10
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• pp.971-978
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• 2013

This work presents a W band frequency synthesizer which is composed of 26 GHz VCO, Phase Locked Loop and frequency tripler using 65 nm RF CMOS process. Frequency tuning range of 26 GHz VCO covers the band from 22.8~26.8 GHz and final output frequency of the tripler is from 74 to 75.6 GHz. The fabricated frequency synthesizer consumes 75.6 mW and its phase noise is -75 dBc/Hz at 1 MHz offset, -101 dBc/Hz 10 MHz offset respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.12
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• pp.941-947
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• 2017

This paper reports a fractional-N phase-locked-loop(PLL) frequency synthesizer that is implemented in a $0.35-{\mu}m$ standard CMOS process and generates a quadrature signal for an FRS terminal. The synthesizer consists of a voltage-controlled oscillator(VCO), a charge pump(CP), loop filter(LF), a phase frequency detector(PFD), and a frequency divider. The VCO has been designed with an LC resonant circuit to provide better phase noise and power characteristics, and the CP is designed to be able to adjust the pumping current according to the PFD output. The frequency divider has been designed by a 16-divider pre-scaler and fractional-N divider based on the third delta-sigma modulator($3^{rd}$ DSM). The LF is a third-order RC filter. The measured results show that the proposed device has a dynamic frequency range of 460~510 MHz and -3.86 dBm radio-frequency output power. The phase noise of the output signal is -94.8 dBc/Hz, and the lock-in time is $300{\mu}s$.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.6
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• pp.100-108
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• 2005

In this paper deals with the frequency control of the HVDC scheme linking Haenam to Cheju Island. The primary aim of the study is to develop and evaluate a new frequency control that can be employed without having to utilise the existing Synchronous Compensators(Gas Turbines). Transient condition studies are performed utilising the detailed control strategies for the HVDC link, implemented in PSCAD/EMTDC. Study cases are completed involving synchronous compensators trip and load ripping events and study plots presented. It is demonstrated that the existing frequency measurement can be replaced by one derived from the AC network alone, incorporated into a new frequency control algorithm and gives effective frequency control and dynamic performance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.9
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• pp.903-911
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• 2014

This paper proposes a high speed frequency synthesizer with dual phase-locked loop(PLL) structure to improve phase noise level and shape in a wideband receiver. To reduce phase noise and fractional spur, a output frequency of $1^{st}$ PLL used as reference frequency of $2^{nd}$ PLL is changed. The frequency synthesizer has been designed with 1 Hz frequency resolution using digital NCO in 6.5~8.5 GHz wide spectrum. The measured results of the fabricated frequency synthesizer show that the output power is about -3 dBm, the maximum lock-in time and phase noise are within 60 us and -95 dBc/Hz at 10 kHz offset, respectively.