• Journal of Advanced Marine Engineering and Technology
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• v.30 no.3
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• pp.444-448
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• 2006

In this paper, a frequency synthesizer for X-band FMCW radars is proposed. Some X-band FMCW radars have been used as a level sensor for tanker ship and the resolution of the level sensor may be mainly depend on linearity of frequency sweep. For a linear frequency sweep. the proposed synthesizer employs a phase-locked loop using prescalars and a high speed digital PLL chip. The measured results show that the linear frequency sweep range is from 10 GHz to 11 GHz and the output power of the synthesizer is minium 7 dBm. and the phase noise is about -80 dBc/Hz at 100 KHz offset from 11 GHz.

• Journal of IKEEE
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• v.17 no.3
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• pp.248-253
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• 2013

Frequency detector is a circuit that converts the frequency to a digital representation and finds its application in various fields such as modulator and synchronization circuitry. In this paper, a couple of first-order and second-order frequency discriminator structures are modeled and analyzed with their quantization noise sources. Also a delta-sigma frequency detector architecture is proposed. Through theoretical analysis and derived equations, the output noise is obtained, which is validated by simulation. The proposed all-digital frequency discriminator may be applied in the feedback path of the all-digital phase-locked loop.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.1
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• pp.41-48
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• 2002

This paper presents a 18-mW, 2.5-㎓ fractional-N frequency synthesizer with l-bit $4^{th}$-order interpolative delta-sigma ($\Delta{\;}$\sum$)modulator to suppress fractional spurious tones while reducing in-band phase noise. A fractional-N frequency synthesizer with a quadruple prescaler has been designed and implemented in a $0.5-\mu\textrm{m}$ 15-GHz $f_t$ BiCMOS. Synthesizing 2.1 GHzwith less than 200 Hz resolution, it exhibits an in-band phase noise of less than -85 dBc/Hz at 1 KHz offset frequency with a reference spur of -85 dBc and no fractional spurs. The synthesizer also shows phase noise of -139 dBc/Hz at an offset frequency of 1.2 MHz from a 2.1GHz center frequency.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.45-53
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• 2007

To recover transmitted signal perfectly at DTV receiver, we have to acquire carrier frequency synchronization to compensate pilot signal which located in wrong position and rotated phase. Also, we need a symbol timing synchronization to compensate sampling timing error. Conventionally, to synchronize symbol timing, we use Gardner's scheme which used in multi-level signal. Gardner's scheme is well known for its sampling the timing error signal from every symbol and it makes easy to detect and keep timing sync in multi-path channel. In this paper, to discuss the problem when the received power level is out of range and we cannot get synchronization information. With this problem, we use 2 step procedures. First, we put a received signal power compensation block before Garder's timing error detector. Second, adaptive loop filter to get a fast synchronization information and averaging loop filter's output value to reduce the amount of jitter after synchronization in PLL(Phased Locked Loop) circuit which is used to get a carrier frequency synchronization and symbol timing synchronization. Using the averaging value, we can estimate offset. Based on offset changing ratio, we can adapt adaptive loop filter to carrier frequency and symbol timing synchronization circuit.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1233-1236
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• 2003

This paper proposes a phase-locked loop (PLL) that achieves one-cycle lock acquisition by employing the lock-acquisition circuit (LAC). The LAC produces the initial analog voltage ( v$_{c}$ ) that corresponds to the input frequency. When the transfer curve of the LAC matches that of the voltage-controlled oscillator (VCO), one-cycle locking can be possible. By HSPICE simulations, the proposed LAC is proved to be applicable to any kinds of PLL [1][2][3].].

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.206-209
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• 2003

본 논문에서 제안하는 알고리즘은 심벌 타이밍 jitter 를 최소화하기 위해 가장 강한 신호를 주기적으로 감시하고, 그 신호를 적응적으로 DLL(Delayed Locked Loop)의 기준 신호로 정한다. 결과적으로 제안된 알고리즘은 DLL 추적 실패를 피할 수 있고, 기존의 알고리즘에 비하여 DLL의 정상 상태 추적 오류가 작다. 모의실험을 통하여 제안된 알고리즘의 정상상태 DLL 추적오류가 작고 다중 경로 상황에서 DLL 추적 실패를 피할 수 있음을 확인 하였다. 따라서 본 논문에서 제안하는 알고리즘은 OFDM 의 시간동기 복원 알고리즘에 적합하다.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.11-12
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• 2012

본 논문에서는 2차 일반화 적분기(Second-Order Generalized Integrator - SOGI)를 이용한 계통 위상각 검출시에 필수 정보인 계통 주파수를 퍼지제어를 통하여 빠르게 추정하고자 한다. DSOGI-FLL의 기존의 방법과는 다르게 비선형 특성이 강한 주파수 동기화의 동특성 모델에 퍼지제어를 적용함으로써 선형화 오차를 줄이고 계통 주파수 추정을 빠르게 할 수 있다. 제안된 방법은 시뮬레이션을 통하여 우수한 성능이 입증된다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.3
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• pp.239-254
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• 1988

In this paper an exciter which performs modulation and amplification is composed of high power(30dBm) VCO(Voltage Controlled Oscillator) using push-pull circuit. Modulation is FSK using PLL(Phase Locked Loop). A single loop PLL synthesizer having sequency range of 42.5-100.5MHz, 25KHz channel spacing and switching time of 1msec converts down the exciter VCO frequency to 1.25MHz. This signal mixed with the FSK modulated signal coming in the phase detector of exciter. The acquisition time of exciter for frequency hoppng is less than 200usec, so the total acquisition time for transmission is less that 1.5msec. There is no need of additional power amplification because power amlifiction by high power VCO is high enough to communicate within near distance. The proposed frequency synthesizer is not complex so it is suitable for low cost slow frequency hopping spread spectrum communication.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.607-608
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• 2006

A CMOS phase-locked loop (PLL) which synthesizes frequencies between $6.336{\sim}8.976GHz$ in steps of 528MHz and settles in approximately 150ns using the 528MHz reference clock is presented. Frequency hopping between the bands in the each mode is critical point to design the PLL in multi-band orthogonal frequency division multiplexing (OFDM) because frequency switching between each band is less than 9.5ns. To achieve the fast loop settling, integer-N PLL that operates with the high reference frequency to meet the settling requirement is implemented. Two PLLs that operate at 9GHz and 528MHz is integrated and shows the band hopping lower than 1ns.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.5
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• pp.863-871
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• 2003

In this paper, we design a high stable Ku-band phase-locked dielectric resonant microwave oscillator with the gate voltage controls of p-HEMT. By adapting the nonlinear equivalent elements which affects phase noise of microwave oscillator, we optimize the nonlinear elements of p-HEMT to have low phase noise operation. Using the scattering parameters according to bias voltages, we designed the gate voltage control microwave dielectric resonant oscillator and phase-locked loop circuits is applied to have the high stable operations. Designed microwave oscillator as a local oscillator of digital microwave communication shows that output power is 9.17dBm at 10.75GHz and it's phase noise is -88dBc/Hz at 10KHz offset frequency.