• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.963-966
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• 2003

This paper proposes a new locking algorithm of the delay locked loop (DLL) which reduces the lock-acquisition time and eliminates false locking problem to enlarge the operating frequency range. The proposed DLL uses the modified phase frequency detector (MPFD) and the modified charge pump (MCP) to avoid the false locking problem. Adopting a new lock detector that measures delay between elects helps the fast lock-acquisition time greatly. The idea has been confirmed by HSPICE simulations in a 0.35-${\mu}{\textrm}{m}$ CMOS process.

• 한국통신학회논문지
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• 제25권4A호
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• pp.586-591
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• 2000

본 논문에서는 새로운 동조형태 방법을 사용한 위상고정 루프(PLL : Phase Locked Loop)의 궤환 성질을 이용하여 K-band용 위상고정 hair-pin 공진 발진기 (PLHRO)를 설계 및 제작하였다. 24.42GHz 위상고정 Hair-pin 공진 발진기는 반송주파수로부터 100KHz, 10KHz 떨어진 곳에서 각각 -86.6dBc/Hz, -76.5dBc/Hz의 위상잡음 특성을 나타내었고 출력은 -0.6dBm 이었다. 또한 -23dBc이하의 기본 주파수 억압특성과 -65dBc의 스퓨리어스 잡음 특성을 나타내었다. 완충증폭기를 포함한 24.42GHz 위상고정 hair-pin 공진 발진기는 반송주파수로부터 100KHz, 10KHz 떨어진 곳에서 각각 -77.34dBc/Hz, -72dBc/Hz의 위상잡음 특성을 나타내었고 출력은 5.6dBm이었다.

• 한국정보통신학회논문지
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• 제8권1호
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• pp.34-40
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• 2004

본 논문에서는 X-band용 저위상잡음을 갖는 위상고정 유전체 공진 발진기를 설계 및 제작하였다. 위상고정 유전체 공진 발진기의 루프대역 내의 위상잡음을 개선하기 위해서 샘플링위상비교기(Sampling Phase Detector)를 사용하여 전압제어 유전체 공진 발진기를 고안정의 기준주파수에 위상 고정시켰으며 루프대역 밖의 위상잡음을 개선하기 위해서 고임피던스 변환기를 이용한 낮은 위상잡음의 전압제어 발진기를 설계하였다. 제작된 위상고정 유전체 공진 발진기는 51.67㏈c의 고조파 억압특성을 가지고 있으며 공급전력은 1.95W 이하를 필요로 한다. 위상잡음은 상온에서 -107.17㏈c/Hz $\circleda$10KHz와 -113.0㏈c/Hz $\circleda$100KHz의 우수한 특성을 나타내었으며 출력전력은 $-20 ∼ +70^{\circ}C$의 온도 범위에서 13.0㏈m${\pm}$0.33㏈의 안정된 특성을 나타내었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.281-286
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• 2007

In this paper, sub-circuits for 24 GHz phase locked 100ps(PLLs) using $0.5{\mu}m$ SiGe HBT are presented. They are 24 Ghz voltage controlled oscillator(VCO), 24 GHz to 12 GHz regenerative frequency divider(RFD) and 12 GHz to 1.5 GHz static frequency divider. $0.5{\mu}m$ SiGe HBT technology, which offers transistors with 90 GHz fMAX and 3 aluminum metal layers, is employed. The 24 GHz VCO employed series feedback topology for high frequency operation and showed -1.8 to -3.8 dBm output power within tuning range from 23.2 GHz to 26 GHz. The 24 GHz to 12 GHz RFD, based on Gilbert cell mixer, showed 1.2 GHz bandwidth around 24 GHz under 2 dBm input and consumes 44 mA from 3 V power supply including I/O buffers for measurement. ECL based static divider operated up to 12.5 GHz while generating divide by 8 output frequency. The static divider drains 22 mA from 3 V power supply.

• Journal of Power Electronics
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• 제16권6호
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• pp.2024-2034
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• 2016

This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a $0.18{\mu}m$ BCD process, and the die area is $3.96mm^2$. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.

• 한국전자통신학회논문지
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• 제4권4호
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• pp.247-252
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• 2009

본 논문은 전하펌프와 클록트리거 회로를 사용하는 프리스케일러가 포함된 UHF RFID 응용을 위한 900MHz Integer-N 방식의 주파수 합성기를 소개한다. 쿼드러처 출력이 가능한 전압제어발진기와 프리스케일러, 위상주파수검출기와 전하펌프 및 아날로그 고정 검출기는 0.35-${\mu}m$ CMOS 공정으로 설계되었다. 주파수 분주기는 verilog-HDL 모듈을 통해 설계되었으며 mixed-mode 시뮬레이션을 통해 디자인을 검증하였다. 전압제어발진기의 동작 주파수영역은 828MHz에서 960MHz이고 위상이 90도 차이나는 쿼드러처 신호를 출력한다. 시뮬레이션 결과로 위상잡음은 100KHz offset 주파수에서 -102dBc/Hz 이었으며, 고착시간은 896MHz에서 928MHz까지 32MHz step을 천이할 때 4us이다.

• 한국군사과학기술학회지
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• 제19권3호
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• pp.379-386
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• 2016

In this paper, phase noise analysis result for 2.4 GHz PLL(phase locked loop) using SPD(sample phase detector) is proposed. It can be used for high performance frequency synthesizer's LO(local oscillator) to extend output frequency range or for LO of offset PLL to reduce a division rate or for clock signal of DDS(direct digital synthesizer). Before manufacturing, theoretical estimation of PLL's phase noise performance should be performed. In order to calculate phase noise of PLL using SPD, Leeson model is used for modeling phase noise of VCO(voltage controlled oscillator) and OCXO(ovened crystal oscillator). After theoretically analyzing phase noise of PLL, optimized loop filter bandwidth was determined. And then, phase noise of designed loop filter was calculated to find suitable OP-Amp. Also, the calculated result of phase noise was compared with the measured one. The measured phase noise of PLL was -130 dBc/Hz @ 10 kHz.

• 전자공학회논문지
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• 제51권2호
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• pp.46-52
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• 2014

본 논문은 다중 이득 제어를 통하여 빠른 lock-time을 갖는 디지털 위상 주파수 검출기 회로를 제안한다. 기준신호와 피드백 신호의 위상 차이가 클 때, 위상 차이가 적으면서 lock에 근접했을 때, lock 이후의 세 경우에 따라 디지털 위상 동기 루프의 이득을 다르게 설정하여 lock-time을 효과적으로 줄일 수 있다. 시뮬레이션 결과를 통해 제안된 기법을 적용함으로써 기존의 단일 이득 제어 구조보다 lock-time을 약 100배 개선시킬 수 있음을 확인하였다.

• Journal of Power Electronics
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• 제11권3호
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• pp.369-374
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• 2011

Usually, a LPF (low pass filter) is used in the feedback loop of a SRF (synchronous reference frame) - PLL (phase locked loop) system because the measured grid voltage contains harmonic distortions and sensor noises. In this paper, it is shown that the cut-off frequency of the LPF should be designed to suppress the harmonic ripples contained in the measured voltage. Also, a new design method for the loop gain of the PI-type controller in the SRF-PLL is proposed with consideration of the dynamics of the LPF. As a result, a better transient response can be obtained with the proposed design method. The LPF frequency and the PI controller gain are designed in coordination according to the steady state and dynamic performance requirements. Furthermore, in the proposed method, the controller gain and the LPF cut-off frequency are changed from their normal value to a transient value when a voltage disturbance is detected. This paper shows the feasibility and usefulness of the proposed methods through the computer simulations and experimental results.

• 한국군사과학기술학회지
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• 제20권5호
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• pp.673-680
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• 2017

In the proposed paper, we designed low noise frequency synthesizer with compact size for Multi-Band. The proposed frequency synthesizer consists of fundamental frequency band(2 GHz) and harmonic frequency band(4 GHz). To improve the phase noise and spurious level of frequency synthesizer, we analyze how the configuration of frequency synthesizer affect the phase noise and design the multi-band's structure. The implemented frequency synthesizer reduce both the phase noise and spurious level. The phase noise is -92.17 dBc/Hz at 1 kHz frequency offset in 2 GHz and -90.50 dBc/Hz at 1 kHz frequency offset in 4 GHz. All spurious signals including fundamental frequency are suppressed at least 20 dBc than the second harmonic frequency.