• Title/Summary/Keyword: frame memory

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Development of A Component and Advanced Model for The Smart PR-CFT Connection Structure (스마트 반강접 (PR) 콘크리트 충전 강재 합성 (CFT) 접합 구조물에 대한 해석모델의 개발)

  • Seon, Woo-Hyun;Hu, Jong-Wan
    • Journal of the Korean Society for Advanced Composite Structures
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    • v.2 no.4
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    • pp.1-10
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    • 2011
  • This study investigates the performance of composite (steel-concrete) frame structures through numerical experiments on individual connections. The innovative aspects of this research are in the use of connections between steel beams and concrete-filled tube (CFT)columns that utilize a combination of low-carbon steel and shape memory alloy (SMA) components. In these new connections, the intent is to utilize the recentering provided by super-elastic shape memory alloy tension bars to reduce building damage and residual drift after a major earthquake. The low-carbon steel components provide excellent energy dissipation. The analysis and design of these structures is complicated because the connections cannot be modeled as being simply pins or full fixity ones they are partial restraint (PR). A refined finite element (FE) model with sophisticated three dimensional (3D) solid elements was developed to conduct numerical experiments on PR-CFT joints to obtain the global behavior of the connection. Based on behavioral information obtained from these FE tests, simplified connection models were formulated by using joint elements with spring components. The behavior of entire frames under cyclic loads was conducted and compared with the monotonic behavior obtained from the 3D FE simulations. Good agreement was found between the simple and sophisticated models, verifying the robustness of the approach.

Multi-Threaded Parallel H.264/AVC Decoder for Multi-Core Systems (멀티코어 시스템을 위한 멀티스레드 H.264/AVC 병렬 디코더)

  • Kim, Won-Jin;Cho, Keol;Chung, Ki-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.11
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    • pp.43-53
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    • 2010
  • Wide deployment of high resolution video services leads to active studies on high speed video processing. Especially, prevalent employment of multi-core systems accelerates researches on high resolution video processing based on parallelization of multimedia software. In this paper, we propose a novel parallel H.264/AVC decoding scheme on a multi-core platform. Parallel H.264/AVC decoding is challenging not only because parallelization may incur significant synchronization overhead but also because software may have complicated dependencies. To overcome such issues, we propose a novel approach called Multi-Threaded Parallelization(MTP). In MTP, to reduce synchronization overhead, a separate thread is allocated to each stage in the pipeline. In addition, an efficient memory reuse technique is used to reduce the memory requirement. To verify the effectiveness of the proposed approach, we parallelized FFmpeg H.264/AVC decoder with the proposed technique using OpenMP, and carried out experiments on an Intel Quad-Core platform. The proposed design performs better than FFmpeg H.264/AVC decoder before the parallelization by 53%. We also reduced the amount of memory usage by 65% and 81% for a high-definition(HD) and a full high-definition(FHD) video, respectively compared with that of popular existing method called 2Dwave.

Performance Evaluation of Embedded Garbage Collectors in CVM Environment (CVM 환경에서 임베디드 가비지 컬렉터의 성능 평가)

  • Cha, Chang-Il;Kim, Sang-Wook;Chang, Ji-Woong
    • The KIPS Transactions:PartA
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    • v.14A no.3 s.107
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    • pp.173-184
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    • 2007
  • Garbage collection in the Java virtual machine is a core function that relieves application programmers of difficulties related to memory management. In this paper, we evaluate and analyze the performance of GenGC and GenRGC, garbage collectors for embedded Java virtual machines. For performance evaluation, we employ CVM, a real embedded Java virtual machine developed by Sun Microsystems, Inc., as a platform and also use a widely-used SpecJVM98 as a set of benchmark programs. To compare the performance of GenGC and GenRGC, we first evaluate the time of garbage collection and the delay time caused by garbage collection. Second, for more detailed performance analysis of GenRGC, we evaluate the time of garbage collection and the delay time caused by garbage collection while changing the sizes of a block and a frame. Third, we analyze the size of storage space required for performing GenRGC, and show GenRGC to be suitable for embedded environment with a limited mont of memory. Since CVM is the most representative one of embedded Java virtual machines, this performance study is quite meaningful in that we can predict the performance of garbage collectors in real application environments more accurately.

A Study on Motion Estimation Encoder Supporting Variable Block Size for H.264/AVC (H.264/AVC용 가변 블록 크기를 지원하는 움직임 추정 부호기의 연구)

  • Kim, Won-Sam;Sohn, Seung-Il
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.10
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    • pp.1845-1852
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    • 2008
  • The key elements of inter prediction are motion estimation(ME) and motion compensation(MC). Motion estimation is to find the optimum motion vectors, not only by using a distance criteria like the SAD, but also by taking into account the resulting number of 비트s in the 비트 stream. Motion compensation is compensate for movement of blocks of current frame. Inter-prediction Encoding is always the main bottleneck in high-quality streaming applications. Therefore, in real-time streaming applications, dedicated hardware for executing Inter-prediction is required. In this paper, we studied a motion estimator(ME) for H.264/AVC. The designed motion estimator is based on 2-D systolic array and it connects processing elements for fast SAD(Sum of Absolute Difference) calculation in parallel. By providing different path for the upper and lower lesion of each reference data and adjusting the input sequence, consecutive calculation for motion estimation is executed without pipeline stall. With data reuse technique, it reduces memory access, and there is no extra delay for finding optimal partitions and motion vectors. The motion estimator supports variable-block size and takes 328 cycles for macro-block calculation. The proposed architecture is local memory-free different from paper [6] using local memory. This motion estimation encoder can be applicable to real-time video processing.

Past Affairs-Related Collective Memories and the Archival Justice : The Contemporary Rebuilding of the Archive on the Truth and Reconciliation Committee (과거사 집단기억과 '아카이브 정의' 진실화해위원회 아카이브의 동시대적 재구성)

  • Lee, Kyong Rae
    • The Korean Journal of Archival Studies
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    • no.46
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    • pp.5-44
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    • 2015
  • This article purposes to define archival justice and suggest democratic modeling of the archive on the Truth and Reconciliation Committee (TRC), which is focused on victims of state violence. These purposes come from critical mind that the absence of framework of the records management for collective memory would cause incorporation of TRC archives into mainstream archives systems in which voices of victims have been marginalized. This article intends to expand theoretical prospects of documentation of past affairs through applying humanistic and theoretical frameworks differently from institutional and policy approaches on restoration of collective memory. In order to do this, this article first considers archival justice as archives building in which state violence' victims are pivotal and then extracts theoretical frameworks for building the archives based on archival justice from recent discourses of post-colonial archives and community archives. As the next step, it criticizes current conditions of TRC archives in Korea on the basis of extracted theoretical frames and finally suggests realistic models in which each theoretical frame could be applied effectively into TRC archives that is focused on victims.

Optimized Hardware Design using Sobel and Median Filters for Lane Detection

  • Lee, Chang-Yong;Kim, Young-Hyung;Lee, Yong-Hwan
    • Journal of Advanced Information Technology and Convergence
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    • v.9 no.1
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    • pp.115-125
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    • 2019
  • In this paper, the image is received from the camera and the lane is sensed. There are various ways to detect lanes. Generally, the method of detecting edges uses a lot of the Sobel edge detection and the Canny edge detection. The minimum use of multiplication and division is used when designing for the hardware configuration. The images are tested using a black box image mounted on the vehicle. Because the top of the image of the used the black box is mostly background, the calculation process is excluded. Also, to speed up, YCbCr is calculated from the image and only the data for the desired color, white and yellow lane, is obtained to detect the lane. The median filter is used to remove noise from images. Intermediate filters excel at noise rejection, but they generally take a long time to compare all values. In this paper, by using addition, the time can be shortened by obtaining and using the result value of the median filter. In case of the Sobel edge detection, the speed is faster and noise sensitive compared to the Canny edge detection. These shortcomings are constructed using complementary algorithms. It also organizes and processes data into parallel processing pipelines. To reduce the size of memory, the system does not use memory to store all data at each step, but stores it using four line buffers. Three line buffers perform mask operations, and one line buffer stores new data at the same time as the operation. Through this work, memory can use six times faster the processing speed and about 33% greater quantity than other methods presented in this paper. The target operating frequency is designed so that the system operates at 50MHz. It is possible to use 2157fps for the images of 640by360 size based on the target operating frequency, 540fps for the HD images and 240fps for the Full HD images, which can be used for most images with 30fps as well as 60fps for the images with 60fps. The maximum operating frequency can be used for larger amounts of the frame processing.

A Real-Time Multiple Circular Buffer Model for Streaming MPEG-4 Media (MPEG-4 미디어 스트리밍에 적합한 실시간형 다중원형버퍼 모델)

  • 신용경;김상욱
    • Journal of KIISE:Computing Practices and Letters
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    • v.9 no.1
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    • pp.13-24
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    • 2003
  • MPEG-4 is a standard for multimedia applications and provides a set of technologies to satisfy the needs of authors, service providers and end users alike. In this paper, we suggest a Real-time Multiple Circular Buffer (M4RM Buffer) model, which is suitable for streaming these MPEG-4 contents efficiently. M4RM buffer generates each structure of the buffer, which matches well with each object composing an MPEG-4 content, according to the transferred information, and manipulates multiple read/write operations only by its reference. It divides the decoder buffer and the composition buffer, which are described in the standard, by the unit of frame allocated to minimize the range of access. This buffer unit of a frame is allocated according to the object description. Also, it processes the objects synchronization within the buffer and provides APIs for an efficient buffer management to process the real-time user events. Based on the performance evaluation, we show that M4RM buffer model decreases the waiting time in a buffer frame, and so allows the real-time streaming of an MPEG-4 content using the smaller size of the memory block than IM1-2D and Window Media Player.

Exploitation of IP-based Intelligent Networked Measuring and Control Device and System

  • Liu, Gui-Xiong;Luo, Yi;Fang, Xiao-Dong
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.1235-1239
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    • 2003
  • On the base of network frame and protocol system of Ethernet the networked sensing technology based on Ethernet is studied and the design principles of industrial Ethernet measurement of control system is put forward, and the general structure model is built in the paper. An eight-bit economical MCU scheme is proposed, and a general scheme of distributed intelligent networked measuring and control equipment based on TCP/IP is designed too. A compact TCP/IP protocol stack are successfully implemented in eight-bit MCU. With C51 program language, method of modularized programming is applied in soft design. The problem of in-system modifying measuring and control strategy of its system is solved successfully by assigning memory dynamically and saving parameter with EEPROM, and it makes the intelligent networked measurement and control system can explain and analyses control strategy from PC. Experiment result shows that, the research of intelligent networked measurement and control equipment and system base on TCP/IP is successful, with flexible network, convenient usage, and good commonality.

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A Multi-Level Accumulation-Based Rectification Method and Its Circuit Implementation

  • Son, Hyeon-Sik;Moon, Byungin
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.11 no.6
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    • pp.3208-3229
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    • 2017
  • Rectification is an essential procedure for simplifying the disparity extraction of stereo matching algorithms by removing vertical mismatches between left and right images. To support real-time stereo matching, studies have introduced several look-up table (LUT)- and computational logic (CL)-based rectification approaches. However, to support high-resolution images, the LUT-based approach requires considerable memory resources, and the CL-based approach requires numerous hardware resources for its circuit implementation. Thus, this paper proposes a multi-level accumulation-based rectification method as a simple CL-based method and its circuit implementation. The proposed method, which includes distortion correction, reduces addition operations by 29%, and removes multiplication operations by replacing the complex matrix computations and high-degree polynomial calculations of the conventional rectification with simple multi-level accumulations. The proposed rectification circuit can rectify $1,280{\times}720$ stereo images at a frame rate of 135 fps at a clock frequency of 125 MHz. Because the circuit is fully pipelined, it continuously generates a pair of left and right rectified pixels every cycle after 13-cycle latency plus initial image buffering time. Experimental results show that the proposed method requires significantly fewer hardware resources than the conventional method while the differences between the results of the proposed and conventional full rectifications are negligible.

Development and Application of a Miniature Stereo-PIV System (Miniature Stereo-PIV 시스템의 개발과 응용)

  • Kim, K.C.;Chetelat, Olivier;Kim, S.H.
    • Transactions of the Korean Society of Mechanical Engineers B
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    • v.27 no.11
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    • pp.1637-1644
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    • 2003
  • Stereoscopic particle image velocimetry is a measurement technique to acquire three dimensional velocity field by two cameras. With a laser sheet illumination, the third velocity component can be deduced from out-of$.$plane velocity components using a stereoscopic matching method. Most industrial fluid flows are three dimensional turbulent flows, so it is necessary to use the stereoscopic PIV measurement method. However the existing stereoscopic PIV system seems hard to use since it is very expensive and complex. In this study we have developed a Miniature Stereo-PIV(MSPIV) system based on the concept of the Miniature PIV system which we have already developed. In this paper, we address the design and some primitive experimental results of the Miniature Stereo-PIV system. The Miniature Stereo-PIV system features relatively modest performances, but is considerably smaller, cheaper and easy to handle. The proposed Miniature Stereo-PIV system uses two one-chip-only CMOS cameras with digital output. Only two other chips are needed, one for a buffer memory and one for an interfacing logic that controls the system. Images are transferred to a personal computer (PC) via its standard parallel port. No extra hardware is required (in particular, no frame grabber board is needed).