• 한국통신학회논문지
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• 제29권1C호
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• pp.72-82
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• 2004

본 논문은 MPEG-2 인트라 (I) 프레임의 더욱 강화된 오류 은닉 기술을 제안한다. MPEG-2 소스 부호화 알고리즘은 가변장 부호화를 사용하기 때문에 채널 오류에 매우 민감하다. 채널에서 발생된 전송 오류는 오류 정정 기술을 사용하여 보정되지만 제대로 보정되지 않은 오류는 디코더에서 오류 은닉 기술을 사용함으로써 시각적 왜곡이 최소화될 수 있다. 또한 GOP의 시작 프레임인 I 프레임의 오류는 움직임 보상 예측 부호화 방식으로 인하여 다른 인터 프레임에 전달되어 더욱 심각한 화질 저하를 가져온다. 본 논문에서 제안하는 오류 은닉 방식은 I 프레임에 발생된 연속적인 슬라이스 오류를 인접한 인터 프레임의 시공간적 정보를 이용하여 기존 방식보다 효과적으로 처리하는 방식이다. 이 방식은 기존의 방식들이 갖는 시간적 그리고 공간적에서 발생하는 단점을 효율적으로 개선할 수 있으며, 전송 오류가 심한 망에서 발생되는 극심한 슬라이스 오류에서도 좋은 시각적 효과를 얻을수 있다. 알고리즘은 MPEG-2 비디오 코덱 범위에서 수행되었으며 모의실험을 통하여 제안된 방식이 다른 방식들보다 높은 PSNR과 개선된 시각적 효과를 확인할 수 있었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.599-602
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• 2002

A new approach of error concealment using a digital watermarking technique for interframe video coding is presented in this paper. In the proposed method, the most important feature of the reference frame is extracted. Then, this feature is embedded into the prediction error of current frame prior to transmission. Error concealment is achieved by means of recovering the erroneous reference frame using the embedded data before the reconstruction of current frame is performed. Simulation results demonstrated the effectiveness of the proposed method.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 D
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• pp.2113-2115
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• 2006

This paper proposes a spatio-temporal correlation algorithm that takes advantage of the spatial and temporal correlations in video streams for error concealment. The spatio-temporal correlation algorithm sets the neighborhood area of the damaged part as a reference window, then finds the area that best matches the reference window in the previous frame. The best-matched area in the previous frame replaces the damaged part in the current frame. The results of ten variations of the proposed algorithm are compared with conventional error concealment methods. These methods include the ones applicable to P-frames as well as I-frames. The comparison results show that the proposed algorithm is very efficient for l-frame error concealment with a large motion between frames.

• 한국기계가공학회지
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• 제3권4호
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• pp.7-12
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• 2004

Inspection and analysis are essential process to determine whether a completed product is in given specification or not. Analysis of products with very complicated shape is difficult to carry out direct comparison between inspected coordinate and designed coordinates. So process called as matching or registrations is needed to solve this problem. By defining error between two coordinates and minimizing the error, registration is done. Registration consists of translation, rotation and scale transformations. Error must be defined to express feature of inspected product. In this paper, registration algorithm is developed to determine pose of sub-frame at assembly with body of automobile by defining error between two coordinates considering geometric feature of sub-frame.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.174-178
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• 2001

An improved stationary frame-based digital current control technique for a permanent magnet (PM) synchronous motor is presented. Generally, the stationary frame current controller is known to provide the advantage of a simple implementation. However, there are some unavoidable limitations such as a steady-state error and a phase delay in the steady-state. On the other hand, in the synchronous frame current regulator, the regulated currents are dc quantities and a zero steady-state error can be obtained through the integral control. However, the need to transform the signals between the stationary and synchronous frames makes the implementation of a synchronous frame regulator complex. Although the PI controller in the stationary frame gives a steady-state error and a phase delay, the control performance can be greatly improved by employing the exact decoupling control inputs for the back EMF, resulting in an ideal steady-state control characteristics irrespective of an operating condition as in the synchronous PI decoupling controller. However, its steady-state response may be degraded due to the inexact cancellation inputs under the parameter variations. To improve the control performance in the stationary frame, the disturbance is estimated using the time delay control. The proposed scheme is implemented on a PM synchronous motor using DSP TMS320C31 and the effectiveness is verified through the comparative simulations and experiments.

• Journal of Power Electronics
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• 제1권2호
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• pp.88-98
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• 2001

An improved stationary frame-based digital current control technique for a permanent magnet(PM) synchronous motor is presented. Generally, the stationary frame current controller is known to provide the advantage of a simple implementation. However, there are some unavoidable limitations such as a steady-state error and a phase delay in the steady-state. On the other hand, in the synchronous frame current regulator the regulated currents are dc quantities and a zero steady-state error can be obtained through the integral control. However, the need to transform the signals between the stationary and synchronous frames makes the implementation of a synchronous frame regulator complex. Although the PI controller in the stationary frame gives a steady-state error and a phase delay, the control performance can be greatly improved by employing the exact decoupling control inputs for the back EMF., resulting in an ideal steady-state control characteristics irrespective of an operating condition as in the synchronous PI decoupling controller. However, its steady-state response may be degraded due to the inexact cancellation inputs under the parameter variations. To improve the control performance in the stationary frame, the disturbance is estimated using the time delay control. The proposed scheme is implemented on a PM synchronous motor using DSP TMS320C31 and the effectiveness is verified through the comparative simulations and experiments.

• 조명전기설비학회논문지
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• 제28권11호
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• pp.68-76
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• 2014

This paper presents an offset error compensation algorithm for the accurate phase angle of the grid voltage in single-phase grid-connected inverters. The offset error generated from the grid voltage measurement process cause the fundamental harmonic component with grid frequency in the synchronous reference frame phase lock loop (PLL). As a result, the grid angle is distorted and the power quality in power systems is degraded. In addition, the dq-axis currents in the synchronous reference frame and phase current have the dc component, first and second order ripples compared with the grid frequency under the distorted grid angle. In this paper, the effects of the offset and scaling errors are analyzed based on the synchronous reference frame PLL. Particularly, the offset error can be estimated from the integrator output of the synchronous reference frame PLL and compensated by using proportional-integral controller. Moreover, the RMS (Root Mean Square) function is proposed to detect the offset error component. The effectiveness of the proposed algorithm is verified through simulation and experiment results.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.927-928
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• 2008

In this paper, a interpolation error concealment algorithm of motion compensated interpolated frame for motion compensated frame rate conversion to reduce the block artifacts caused by failure of conventional motion estimation based on block matching algorithm is proposed. Experimental results show good performance of the proposed scheme with significant reduction of the block artifacts.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 심포지엄 논문집 정보 및 제어부문
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• pp.84-86
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• 2006

An informed watermarking algorithm is proposed in this work that aids in concealing packet loss errors in video communications. This watermark-based error concealment(WEC) method embeds a low resolution version of the video frame inside itself as watermark data. At the receiver, the extracted watermark is used as a reference for error concealment. The proposed DCT-based algorithm has features of informed watermarking in order to minimize the distortion of the host frame. At the encoder, a predictive feedback loop Is employed which helps to adjusts the strength of the scale factor Furthermore, some of the modified coefficients of the DCT signal are virtually free from distortion by employing bit- sign adaptivity. The performance of the detector is Qualitatively analyzed for error concealment applications where full-frame DCT embedding proved to be more advantageous.

• 융합신호처리학회논문지
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• 제4권2호
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• pp.31-39
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• 2003

MPEG-2 소스 부호화 알고리즘은 가변장 부호화를 사용하기 때문에 채널 오류에 매우 민감하다. 압축 데이터가 전송되는 동안 비트 오류가 발생하게 되고, 이 오류를 정정 기술로 보정할 수 없는 경우 디코더에서는 오류 은닉 방식을 사용함으로써 영상의 화질 저하를 최소화할 수 있다. 본 논문에서 제안하는 알고리즘은 I 프레임의 연속적인 매크로블록 오류를 은닉하기 위한 방식으로 I 프레임과 시간적으로 가장 가까이 위치한 이전 GOP의 B 프레임의 시간적 정보와 P 프레임의 공간적 정보를 이용한다. 이 방식은 기존의 오류 은닉 방식들이 갖는 시간적 오류에 의한 움직임 왜곡과 공간적 오류에 의한 번짐 현상을 개선할 수 있으며, 전송 오류가 매우 심한 망에서의 심각한 슬라이스 오류를 보다 효과적으로 은닉할 수 있다. 알고리즘은 MPEG-2 비디오 코덱에서 수행되었고 모의 실험을 통하여 다른 방식들에 비하여 I 프레임의 슬라이스 오류를 효율적으로 은닉할 수 있음을 증명한다.