• 제어로봇시스템학회:학술대회논문집
• /
• 2000.10a
• /
• pp.259-259
• /
• 2000

In the recent, the size of hardware is smaller and the structure is simpler, without reducing the performance of the digital controller. Accordingly, the fixed-point arithmetic is very important in the digital controller. This paper presents simulation to apply the robust control algorithms to DVDR servo controller using the floating-point and fixed-point arithmetic from the matlab. Also, it analyses and compares the performance of control algorithms in the each of point calculation and presents a method for improvement of drop in the performance, quantization error and overflow/underflow from using the fixed-point arithmetic

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.11 no.1
• /
• pp.175-181
• /
• 2010

In this paper, we propose a novel hardware architecture for Rate control module for real time full HD video compression. In the proposed architecture, QP is updated by using the rate control algorithm to every the macroblock line(120MB for Full HD, 20MB for CIF image). Since there are many complex arithmetic and floating point arithmetic in rate control algorithm of JM for H.264, it is impossible to process the rate control algorithm using the integer arithmetic CPU core. So we adopted floating point arithmetic unit in our architecture, and implemented the rate control algorithm using the floating unit. With this implemented hardware, the implemented hardware is verified to be operated in real time.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.12
• /
• pp.2921-2926
• /
• 2013

In this paper, a decimal floating-point arithmetic unit(DFP) was proposed and redesigned to support high speed arithmetic operation employed parallel processing technique. The basic architecture of the proposed DFP was based on the L.K.Wang's DFP and improved it enabling high speed operation by parallel processing for two operands with same size of exponent. The proposed DFP was synthesized as a target device of xc2vp30-7ff896 using Xilinx ISE and verified by simulation using Flowrian tool of System Centroid co. Compared to L.K.Wang's DFP and reference [6]'s method, the proposed DFP improved data processing speed about 8.4% and 3% respectively in case of same input data.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.20 no.4
• /
• pp.24-29
• /
• 1983

In this paper, a floating-point processor which satisfied the subset of the proposed IEEE standard has been designed and realized by TTL chips. This processor consists of a floating-point arithmetic unit and a control sequencer. AHPL has been used in the design of sequencer. The execution times for the arithmetic operations were measured and compared with other microprocessor. The results had shown faster operations compared to the Z-80 processor. Though this processor was built by TTL chips, it could be fabricated as a one-chip processor.

• Proceedings of the KIEE Conference
• /
• 1999.11c
• /
• pp.788-790
• /
• 1999

A software implementation of floating-point addition and multiplication is presented. For this, the ANSI/IEEE standard for binary floating-point arithmetic is reviewed briefly. The architecture and behavior of the $Intel^{(R)}\;80{\times}87$ FPU is fully studied and basic algorithms for floating-point addition and multiplication are used for the implementation. Some examples and their verifications are also presented.

• Proceedings of the IEEK Conference
• /
• 2000.06b
• /
• pp.250-253
• /
• 2000

In this paper, we Implement a new arithmetic computation for MPEG audio data to overcome the limitations of real number processing in the fixed-point arithmetics, such as: overheads in processing time and power consumption. We aims at efficiently dealing with real numbers by extending the fixed-point arithmetic manipulation for floating-point numbers in MPEG audio data, and implementing the DSP libraries to support the manipulation and computation of real numbers with the fixed-point resources.

• Structural Engineering and Mechanics
• /
• v.37 no.6
• /
• pp.633-648
• /
• 2011

This paper investigates the aspect-ratio locking of the isoparametric 8-node quadrilateral (QUAD8) element. An important finding is that, if finite element solution is carried out with in exact arithmetic (i.e., with no truncation and round off errors), the locking tendency of the element is completely avoided even for aspect-ratios as high as 100000. The current finite element codes mostly use floating point arithmetic. Thus, they can only avoid this locking for aspect-ratios up to 100 or 1000. A novel method is proposed in the paper to avoid aspect-ratio locking in floating point computations. In this method, the offending terms of the strain-displacement matrix (i.e., $\mathbf{B}$-matrix) are multiplied by suitable scaling factors to avoid ill-conditioning of stiffness matrix. Numerical examples are presented to demonstrate the efficacy of the method. The examples reveal that aspect-ratio locking is avoided even for aspect-ratios as high as 100000.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2010.04a
• /
• pp.49-52
• /
• 2010

디지털 신호처리 알고리즘들은 실제 시스템에 적용할 때 임베디드 시스템 등 하드웨어의 성능과 소비전력 및 비용에 제약이 있을 경우 연산 정밀도가 높은 floating-point 연산 대신 제한된 정밀도와 적은 연산 비용을 요구하는 fixed-point 연산을 사용하여 구현한다. 시스템의 개발단계에서는 적용할 알고리즘을 floating-point 연산을 이용한 코드를 먼저 작성한 후 이를 fixed-point 연산으로 대체하는 과정을 거치게 되는데, 이는 숙련된 개발자와 상당한 양의 개발기간을 요하는 까다로운 작업이다. 이에 본 연구에는 코드작성 편의를 높이고 개발기간을 단축하기 위해 C++ template 기반의 fixed-point 연산 라이브러리를 개발하였다. 이는 floating-point 연산 코드와 fixed-point 연산 코드를 별도로 개발할 필요 없이 하나의 코드를 이용하여 자유로이 연산 정밀도를 지정할 수 있으며 개발자는 기존의 floating-point 연산을 이용하는 코드를 작성하는 것처럼 쉽게 코드를 작성할 수 있도록 한다. 또한, template 기반으로 작성되어 기존의 연구들과 달리 추가적인 작업도구 없이도 범용 C++ 컴파일러가 최적화된 코드를 생성할 수 있도록 되어있는 것이 특징이다.

• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.39 no.2
• /
• pp.1-5
• /
• 2002

Floating point unit system follows IEEE 754 Standard. In this paper, we used 1's complement system instead of 2's complement to practice the arithmetic. By converting we enable this system to compute simply and fast. To improve the speed of newly design adder, we used a transformation Carry selector adder of 53 bits. In paper, a design of floating point unit high efficiency micro processor system about for high speed. 

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.3
• /
• pp.20-25
• /
• 2009

We propose hardware architecture of floating-point square root and inverse square root arithmetic units using lookup tables. They are used for lighting engines and shader processor for 3D graphic processing. The architecture is based on Taylor series expansion and consists of lookup tables and correction units so that the size of look-up tables are reduced. It can be applied to 32 bit floating point formats of IEEE-754 and reduced 24 bit floating point formats. The square root and inverse square root arithmetic units for 32 bit and 24 bit floating format number are designed as the proposed architecture. They can operation in a single cycle, and satisfy the precision of $10^{-5}$ required by OpenGL 1.x ES. They are designed using Verilog-HDL and the RTL codes are verified using an FPGA.