• Journal of Korea Spatial Information System Society
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• v.11 no.2
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• pp.133-142
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• 2009

Recently, with the advance of wireless internet and the frequent use of mobile devices, demand for LBS(Location Based Service) is increasing, and research is required on spatial indexes for the storage and maintenance of spatial data to provide efficient LBS in mobile device environments. In addition, the use of flash memory as an auxiliary storage device is increasing in order to store large spatial data in a mobile terminal with small storage space. However, the application of existing spatial indexes to flash-memory lowers index performance due to the frequent updates of nodes. To solve this problem, research is being conducted on flash-memory based spatial indexes, but the efficiency of such spatial indexes is lowered by low utilization of buffer and flash-memory space. Accordingly, in order to solve problems in existing flash-memory based spatial indexes, this paper proposed FR-Tree (Flash-Memory based R-Tree) that uses the node compression technique and the delayed write operation technique. The node compression technique of FR-Tree increased the utilization of flash-memory space by compressing MBR(Minimum Bounding Rectangle) of spatial data using relative coordinates and MBR size. And, the delayed write operation technique reduced the number of write operations in flash memory by storing spatial data in the buffer temporarily and reflecting them in flash memory at once instead of reflecting the insert, update and delete of spatial data in flash-memory for each operation. Especially, the utilization of buffer space was enhanced by preventing the redundant storage of the same spatial data in the buffer. Finally, we perform ed various performance evaluations and proved the superiority of FR-Tree to the existing spatial indexes.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.10
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• pp.1529-1534
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• 2013

Since a NAND-flash memory is able to store mass data in a small sized chip and consumes low power, it is exploited on various hand-held devices, such as a smart phone and a sensor node, etc. To process efficiently mass data stored in the flash memory, it is required to use an index. However, since the write operation of the flash memory is slower than the read operation and an overwrite operation is not supported, the usage of existing index schemes degrades the performance of the index. In this paper, we survey the previous researches of index schemes for the flash memory and classify the researches by the methods to solve problems. We also present the performance factor to be considered when we design the index scheme on the flash memory.

• Journal of the Korea Society of Computer and Information
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• v.22 no.9
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• pp.1-8
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• 2017

In this paper, we propose a file system for flash memory which remedies shortcomings of existing flash memory file systems. Besides supporting large block size, the proposed file system reduces time in initializing file system significantly by adopting logical address comprised of erase block number and bitmap for pages in the block to find a page. The file system is suitable for embedded systems with limited main memory since it has small in-memory data structures. It also provides efficient management of obsolete blocks and free blocks, which contribute to the reduction of file update time. Finally the proposed file system can easily configure the maximum file size and file system size limits, which results in portability to emerging larger flash memories. By conducting performance evaluation studies, we show that the proposed file system can contribute to the performance improvement of embedded systems.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.26-31
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• 2002

To realize a high integrated Flash memory utilizing SONOS memory devices, the NOR type 1TC(one Transistor Cell) SONOS Flash arrays are fabricated and characterized. This SONOS Flash arrays with common source lines are designed and fabricated by conventional 0.35$\mu\textrm{m}$ CMOS process. The thickness of ONO for memory cell is tunnel oxide of 34${\AA}$, nitride of 73${\AA}$ and blocking oxide of 34${\AA}$. To investigate operating characteristics, CHEI(Channel Hot Electron Injection) method and Bit line erase method are selected as the write operation and the erase method, respectively. The disturbance characteristics according to the write/erase/read cycling are also examined. The degradation characteristics are investigated and then the reliability of SONOS flash memory is guaranteed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.5
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• pp.372-377
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• 2003

To realize a high integrated flash memory utilizing SONOS memory devices, the NOR type ITC(one Transistor Cell) SONOS flash arrays are fabricated and characterized. This SONOS flash arrays with the common source lines are designed and fabricated by conventional 0.35$\mu\textrm{m}$ CMOS process. The thickness of ONO for memory cells is tunnel oxide of 34${\AA}$, nitride of 73${\AA}$ and blocking oxide of 34${\AA}$ . To investigate operating characteristics, CHEI(Channel Hot Electron Injection) method and bit line method are selected as the program and 4he erase operation, respectively. The disturbance characteristics ,according to the program/erase/read cycling are also examined. The degradation characteristics are investigated and then the reliability of SONOS flash memory is guaranteed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.58-61
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• 2010

In this paper, we research the method for HDD I/O Performance improvement by Filter Driver &NAND FLASH Memory. We analyze the effect of the operation of the Device Driver & NAND FLASH Memory and propose the method for the HDD I/O Performance improvement.

• The KIPS Transactions:PartA
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• v.12A no.7 s.97
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• pp.621-626
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• 2005

Recently, flash memory is widely used in various embedded applications since it has many advantages in terms of non-volatility, fast access speed, shock resistance, and low power consumption. However, it requires a software layer called FTL(Flash Translation Layer) due to its hardware characteristics. We present a new FTL algorithm named LSTAFF(Large State Transition Applied Fast flash Translation Layer) which is designed for large block flash memory The presented LSTAFF is adjusted to flash memory with pages which are larger than operating system data sector sizes and we provide performance results based on our implementation of LSTAFF and previous FTL algorithms using a flash simulator.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.191-193
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• 2005

Flash memories are one of best media to support portable computer's storages. However, we need to improve traditional data management scheme due to the relatively slow characteristics of flash operation as compared to RAM memory. In order to achieve this goal, we devise a new scheme called Flash Two Phase Locking (F2PL) scheme for efficient data processing. F2PL improves transaction performance by allowing multi version reads and efficiently handling slow flash write/erase operation in lock management process.

• The KIPS Transactions:PartA
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• v.14A no.1 s.105
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• pp.39-46
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• 2007

Recently flash memory is widely accepted as a storage devise of embedded systems for portability and performance reasons. Flash memory has many distinguishing features compared to legacy magnetic disks. Especially, a file system for flash memory usually assumes the form of log-structured file system and it employs garbage collector accordingly. Since the garbage collector can greatly affect the performance of file system, it should be designed carefully considering flash memory features. In this paper, we suggest a new garbage collector for existing JFFS2 (Journaling Flash File System II) file system. By extensive performance evaluation, we show that the proposed garbage collector achieves improved performance in terms of flash memory consumption rate, increased flash memory life time, and improved wear-leveling.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.87-96
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• 2019

Low power issue is one of the most critical problems in the Internet of Things (IoT), which are powered by battery. To solve this problem, various approaches have been presented so far. In this paper, we propose a method to reduce the power consumption by reducing the numbers of accesses into the flash memory consuming a large amount of power for on-chip software execution. Our approach is based on using cooperative logging structure to distribute the sampling overhead in single sensor node to adjacent nodes in case of rare-event applications. The proposed algorithm to identify event occurrence is newly introduced with negative feedback method by observing difference between past data and recent data coming from the sensor. When an event with need of flash access is determined, the proposed approach only allows access to write the sampled data in flash memory. The proposed event detection algorithm (EDA) result in 30% reduction of power consumption compared to the conventional flash write scheme for all cases of event. The sampled data from the sensor is first traced into the random access memory (RAM), and write access to the flash memory is delayed until the page buffer of the on-chip flash memory controller in the micro controller unit (MCU) is full of the numbers of the traced data, thereby reducing the frequency of accessing flash memory. This technique additionally reduces power consumption by 40% compared to flash-write all data. By sharing the sampling information via LoRa channel, the overhead in sampling data is distributed, to reduce the sampling load on each node, so that the 66% reduction of total power consumption is achieved in several IoT edge nodes by removing the sampling operation of duplicated data.