• 전기학회논문지
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• 제59권6호
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• pp.1095-1102
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• 2010

This paper presents an equalizer reducing CCI(cell-to-cell interference) in MLC NAND flash memory. High growth of the flash memory market has been driven by two combined technological efforts that are an aggressive scaling technique which doubles the memory density every year and the introduction of MLC(multi level cell) technology. Therefore, the CCI is a critical factor which affects occurring data errors in cells. We introduced an equation of CCI model and designed an equalizer reducing CCI based on the proposed equation. In the model, we have been considered the floating gate capacitance coupling effect, the direct field effect, and programming methods of the MLC NAND flash memory. Also we design and verify the proposed equalizer using Matlab. As the simulation result, the error correction ratio of the equalizer shows about 20% under 20nm NAND process where the memory channel model has serious CCI.

• 한국멀티미디어학회논문지
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• 제13권9호
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• pp.1272-1284
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• 2010

모바일 컴퓨터가 고성능화되고 범용 컴퓨터처럼 사용되면서 모바일 컴퓨터의 운영체제에서도 주 기억장치를 효율적으로 사용할 수 있게 해주는 스왑 시스템 기능이 요구되고 있다. 모바일 컴퓨터의 저장 장치는 플래시 메모리가 널리 쓰이고 있는데 현재의 리눅스 스왑 시스템은 플래시 메모리를 고려하지 않고 있다. 스왑 시스템은 실행 중인 프로세스의 내용을 저장하기 때문에 프로세스 실행과 밀접한 관련이 있다. 이러한 성질을 고려하여, 본 논문에서는 프로세스 별로 플래시 메모리 블록을 할당하는 PASS(Process-Aware Swap System)라는 새로운 리눅스 스왑 시스템을 연구하였다. 트레이스 기반의 실험을 통해 PASS의 가비지 수집 성능이 기존 가비지 수집 기법을 사용하는 리눅스 스왑 시스템보다 우수함을 보였다.

• Journal of Information Technology Applications and Management
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• 제12권4호
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• pp.59-70
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• 2005

Flash memories are one of best media to support portable computer's storages in mobile computing environment. The features of non-volatility, low power consumption, and fast access time for read operations are sufficient grounds to support flash memory as major database storage components of portable computers. However, we need to improve traditional transaction management scheme due to the relatively slow characteristics of flash operation as compared to RAM memory. in order to achieve this goal, we devise a new scheme called Flash Two Phase Locking (F2PL) scheme for efficient transaction processing. F2Pl improves transaction performance by allowing multi version reads and efficiently handling slow flash write/erase operation in lock management process. We also propose a simulation model to show the performance of F2PL. Based on the results of the performance evaluation, we conclude that F2PL scheme outperforms the traditional scheme.

• Journal of Computing Science and Engineering
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• 제8권3호
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• pp.157-172
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• 2014

Contemporary embedded systems often use NAND flash memory instead of hard disks as their swap space of virtual memory. Since the read/write characteristics of NAND flash memory are very different from those of hard disks, an efficient page replacement algorithm is needed for this environment. Our analysis shows that temporal locality is dominant in virtual memory references but that is not the case for write references, when the read and write references are monitored separately. Based on this observation, we present a new page replacement algorithm that uses different strategies for read and write operations in predicting the re-reference likelihood of pages. For read operations, only temporal locality is used; but for write operations, both write frequency and temporal locality are used. The algorithm logically partitions the memory space into read and write areas to keep track of their reference patterns precisely, and then dynamically adjusts their size based on their reference patterns and I/O costs. Without requiring any external parameter to tune, the proposed algorithm outperforms CLOCK, CAR, and CFLRU by 20%-66%. It also supports optimized implementations for virtual memory systems.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 춘계학술대회
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• pp.436-439
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• 2011

휴대용 디지털 기기 보급의 확산되면서 휴대용 저장장치 수요가 급증하고 있으며, 디지털 카메라 및 캠코더에서는 대부분 SD 메모리 카드를 이용하고 있다. SD 메모리 카드는 일반적으로 플래시 메모리를 기반으로 사용자 데이터를 저장한 후 PC에 데이터를 복사하는 형태로 사용되고 있다. 본 논문에서는 플래시 메모리에 데이터를 저장하는 방식이 아닌, 네트워크를 통하여 사진 및 영상 데이터 저장을 할 수 있는 SD 메모리 카드를 제안한다. SD Slave IP를 통해서 들어오는 데이터 및 메모리 주소 값들을 플래시 메모리로 보내지 않고 네트워크 서버에 전달하여, 실시간으로 SD 메모리에 저장할 데이터를 안전하고 편리하게 저장할 수 있다.

• 한국컴퓨터정보학회논문지
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• 제22권4호
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• pp.25-32
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• 2017

Recently, the use of NAND flash memory is being increased as a secondary device to displace conventional magnetic disk. NAND flash memory, as one among non-volatile memories, has many advantages such as low power, high reliability, low access latency, and so on. However, NAND flash memory has disadvantages such as erase-before-write, unbalanced operation speed, and limited P/E cycles, unlike conventional magnetic disk. To solve these problems, NAND flash memory mainly adopted FTL (Flash Translation Layer). In particular, garbage collection technique in FTL tried to improve the system lifetime. However, previous garbage collection techniques have a sensitive property of the system lifetime according to write pattern. To solve this problem, we propose BSGC (Balanced Selection-based Garbage Collection) technique. BSGC efficiently selects a victim block using all intervals from the past information to the current information. In this work, SFL (Search First linked List), as the proposed block allocation policy, prolongs the system lifetime additionally. In our experiments, SFL and BSGC prolonged the system lifetime about 12.85% on average and reduced page migrations about 22.12% on average. Moreover, SFL and BSGC reduced the average response time of 16.88% on average.

• 대한임베디드공학회논문지
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• 제13권3호
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• pp.151-160
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• 2018

NAND flash memories have the advantages of fast access speed, high density and low power consumption, thus they have increasing demand in embedded system and mobile environment. Despite the low power and fast speed gains of NAND flash memory, DRAM disk buffers were used because of the performance load and limited durability of NAND flash cell. However, DRAM disk buffers are not suitable for limited energy environments due to their high static energy consumption. In this paper, we propose WAP-LRU (Write pattern Analysis based Placement by LRU) hybrid disk buffer management policy. Our policy designates the buffer location in the hybrid memory by analyzing write pattern of the workloads to check the continuity of the page operations. In our simulation, WAP-LRU increased the lifetime of NAND flash memory by reducing the number of garbage collections by 63.1% on average. In addition, energy consumption is reduced by an average of 53.4% compared to DRAM disk buffers.

• 한국멀티미디어학회논문지
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• 제12권12호
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• pp.1710-1717
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• 2009

Flash memory has become the most important storage media in mobile devices along with its attractive features such as low power consumption, small size, light weight, and shock resistance. However, a flash memory can not be written before erased because of its erase-before-write characteristic, which lead to some garbage collection when there is not enough space to use. In this paper, we propose a novel garbage collection scheme, called block-level buffer garbage collection. When it is need to do merge operation during garbage collection, the proposed scheme does not merge the data block and corresponding log block but also search the block-level buffer to find the corresponding block which will be written to flash memory in the next future, and then decide whether merge it in advance or not. Our experimental results show that the proposed technique improves the flash performance up to 4.6% by reducing the unnecessary block erase numbers and page copy numbers.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.566-571
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• 2014

Channel-stacked 3D NAND flash memory is very promising candidate for the next-generation NAND flash memory. However, there is an inherent issue on cell size variation between stacked channels due to the declined etch slope. In this paper, the effect of the cell variation on the incremental step pulse programming (ISPP) characteristics is studied with 3D TCAD simulation. The ISPP slope degradation of elliptical channel is investigated. To solve that problem, a new programming method is proposed, and we can alleviate the $V_T$ variation among cells and reduce the total programming time.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 심포지엄 논문집 정보 및 제어부문
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• pp.267-269
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• 2006

Recently, flash memories are one of best media to support portable computer's storages in mobile computing environment. The features of non-volatility, low power consumption, and fast access time for read operations are sufficient grounds to support flash memory as major database storage components of portable computers. However, we need to improve traditional Indexing scheme such as B-Tree due to the relatively slow characteristics of flash operation as compared to RAM memory. In order to achieve this goal, we devise a new indexing scheme called F-Tree. F-Tree improves tree operation performance by compressing pointers and keys in tree nodes and rewriting the nodes without a slow erase operation in node insert/delete processes.