• The KIPS Transactions:PartB
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• v.16B no.2
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• pp.151-156
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• 2009

This paper proposes a Gaussian mixture model(GMM)-based music discrimination system for FM broadcasting. The objective of the system is automatically archiving music signals from audio broadcasting programs that are normally mixed with human voices, music songs, commercial musics, and other sounds. To improve the system performance, make it more robust and to accurately cut the starting/ending-point of the recording, we also added a post-processing module. Experimental results on various input signals of FM radio programs under PC environments show excellent performance of the proposed system. The fixed-point simulation shows the same results under 3MIPS computational power.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.6
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• pp.147-155
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• 1989

In this paper, a real-time implementation of the TWS(track-while-scan) system using the high-speed DSP (digital signal processor) TMS320C25 is described. First, attempts have been made to investigate the FWL (finite word length) effect, which is caused by employing a fixed point arithmetic, of implementing the Kalman filter. The real-time TWS system consists of TWS arithmetic unit, scan converter, and system controller. In addition, the TWS system is in tegrated in the Multi-Bus. In experiment, it is observed that by employing the floating point arithmetic the computation time of 0.35sec is required for tracking 8 targets simultaneously, while 0.28sec is required for the fixed point arithmetic. Since the TWS system is designed to track up to 8 targets simultaneously, we conclude that the system is enough to process Kalman filter in a real-time.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.149-155
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• 2007

In this paper, we propose an real-time implementation of JPEG2000 codec on the ARM9 processor. The implemented codec is designed to separate control codes from data management codes in order to use effectively the system resources such as processor and memory. Especially, in embedded situations like cellular phones it is very important to provide good services using limited processor and internal memory. Since ARM9 series processors do not provide floating-point, large amount of computational time is required to perform the operation which needs highly repetitive floating-point computations like DWT(discrete wavelet transform). The proposed codec was programed using fixed-point to overcome this weakness. Also code optimization considering cache memory was applied to further improve the computational speed.

• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.51-54
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• 2000

This paper describes the fixed-point DSP implementation of a CELP(code-excited linear prediction)-based speech coder. The effective realization methodologies to maximize the utilization of the DSP's architectural features, specifically Parallel movement and pipelining are also presented together with the implementation results targeted for the ITU-T standard G.723.1 using Motorola DSP56309. The operation of the implemented speech coder is verified using the test vectors offered by the standard as well as using the peripheral interface circuits designed for the coder's real-time operation.

• Speech Sciences
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• v.7 no.2
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• pp.225-234
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• 2000

This paper describes the fixed-point DSP implementation of a CELP(Code-excited linear prediction)-based speech coder. The effective realization methodologies to maximize the utilization of the DSP's architectural features, specifically parallel movement and pipelining are also presented together with the implementation results targeted for the ITU-T standard G.723.1 using Motorola DSP56362. The operation of the implemented speech coder is verified using the test vectors offered by the standard as well as using the peripheral interface circuits designed for the coder's real-time operation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.7C
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• pp.962-970
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• 2004

This paper presents an efficient implementation of the 2.4 kbps EHSX(Enhanced Harmonic Stochastic Excitation) speech coder on a TMS320C6701$^{TM}$ floating-point digital signal processor. The EHSX speech codec is based on a harmonic and CELP(Code Excited Linear Prediction) modeling of the excitation signal respectively according to the frame characteristic such as a voiced speech and an unvoiced speech. In this paper, we represent the optimization methods to reduce the complexity for real-time implementation. The complexity in the filtering of a CELP algorithm that is the main part for the EHSX algorithm complexity can be reduced by converting program using floating-point variable to program using fixed-point variable. We also present the efficient optimization methods including the code allocation considering a DSP architecture and the low complexity algorithm of harmonic/pitch search in encoder part. Finally, we obtained the subjective quality of MOS 3.28 from speech quality test using the PESQ(perceptual evaluation of speech quality), ITU-T Recommendation P.862 and could get a goal of realtime operation of the EHSX codec.c.

• The Journal of the Acoustical Society of Korea
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• v.20 no.8
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• pp.19-23
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• 2001

DSP-based implementation is pervasive in wireless communication parts for systems and handsets according to developing high-speed and low-power programmable Digital Signal Processor (DSP). In this paper, we present a real-time implementation of multi-channel Adaptive Multi-rate (AMR) speech coder. The real-time implementation of an AMR algorithm is achieved using 32-bit fixed-point TMS320C6202 DSP chip that operates at 250 MHz. We performed cross compile, linear assembly optimization and TMS320C62xx assembly optimization for real-time implementation. Furthermore, speech data input/output function and communication function with external CPU is included in an AMR speech coder. The AMR Speech coder developed using DSP EVM board was evaluated in ETRI IMT-2000 Test-bed system.

• The KIPS Transactions:PartB
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• v.13B no.4 s.107
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• pp.429-438
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• 2006

Neural Networks(NNs) are applied for solving a wide variety of nonlinear problems in several areas, such as image processing, pattern recognition etc. Although NN can be simulated by using software, many potential NN applications required real-time processing. Thus they need to be implemented as hardware. The hardware implementation of multi-layer perceptrons(MLPs) in several kind of NNs usually uses a fixed-point arithmetic due to a simple logic operation and a shorter processing time compared to the floating-point arithmetic. However, the fixed-point arithmetic-based MLP has a drawback which is not able to apply the MLP software that use floating-point arithmetic. We propose a design method for MLPs which has the floating-point arithmetic-based fully-pipelining architecture. It has a processing speed that is proportional to the number of the hidden nodes. The number of input and output nodes of MLPs are generally constrained by given problems, but the number of hidden nodes can be optimized by user experiences. Thus our design method is using optimized number of hidden nodes in order to improve the processing speed, especially in field of a repeated processing such as image processing, pattern recognition, etc.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.11B
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• pp.1957-1965
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• 2000

본 논문에서는 휴대 멀티미디어 응용을 위한 MDSP(Multimedia Fixed Point DSP) 칩의 내장 메모리 테스트와 기판 수준의 테스트를 지원하기 위해 내장 메모리 테스트를 위한 자체 테스트 기법, 기판 수준의 테스트 지원 및 내장 메모리를 위한 자체 테스트 회로를 제어하기 위한 경계 주사 기법을 구현하였다. 본 논문에서 구현한 기법들은 Verilog HDL을 이용하여 회로들을 설계하였으며, Synopsys 툴과 현대 heb60 라이브러리를 이용하여 합성하였다. 그리고 회로 검증을 위한 시뮬레이터는 Cadence사의 VerilogXL을 사용하였다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.5
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• pp.25-32
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• 1998

In this paper, SA (shape adaptive)-DCT is implemented using a datapath with 4 MACs (multiplication & accumulator). DCT is a well-known bottleneck of real-time video compression using MPEG-like schemes. High-speed pipelined MACs presented here implement real-time DCT. A datapath in this paper executes DCT/IDCT algorithms for QCIF 15fps(frame per second), maximum rate of VLBV(very low bitrte video) in MPEG-4. A 32bit accumulator in a MAC prevents distortion caused by fixed-point process. It can be applied to various operations such as ME (motion estimation) and MC(motion compensation) with a absolutor and a halfer.