• The Journal of the Acoustical Society of Korea
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• v.23 no.5
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• pp.420-427
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• 2004

This paper presents real time implementation of 4kbps EHSX (Enhanced Harmonic Stochastic Excitation) speech coder that combines the harmonic vector excitation coding with time-separated transition coding. The harmonic vector excitation coding uses the harmonic excitation coding for voiced frames and used the vector excitation coding with the structure of analysis-by-synthesis for unvoiced frames, respectively. For transition frames mixed with voiced and unvoiced signal, we use the time-separated transition coding. In this paper. we present the optimization methods of implementation speech coder on the EMS320C6701/sup (R)/ DSP. To reduce the complex for real-time implementation. we perform the optimization method in algorithm by replacing the complex sinusoidal synthesis method with IFFT. and we apply fully pipelines hand assembly coding after converting it from floating source to fixed source. To generate a more efficient code. we also make use or the available EMS320C6701/sup (R)/ resources such as Fastest67x library and memory organization.

• The Journal of the Acoustical Society of Korea
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• v.20 no.1
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• pp.56-61
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• 2001

This paper presents the real-time implementation of an AMR (Adaptive Multi Rate) vocoder which is included in the asynchronous International Mobile Telecommunication (IMT)-2000 mobile ASIC. The implemented AMR vocoder is a multi-rate coder with 8 modes operating at bit rates from 12.2kbps down to 4.75kbps. Not only the encoder and the decoder as basic functions of the vocoder are implemented, but VAD (Voice Activity Detection), SCR (Source Controlled Rate) operation and frame structuring blocks for the system interface are also implemented in this vocoder. The DSP for AMR vocoder implementation is a 16bit fixed-point DSP which is based on the TeakLite core and consists of memory block, serial interface block, register files for the parallel interface with CPU, and interrupt control logic. Through the implementation, we reduce the maximum operating complexity to 24MIPS by efficiently managing the memory structure. The AMR vocoder is verified throughout all the test vectors provided by 3GPP, and stable operation in the real-time testing board is also proved.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.5
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• pp.857-864
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• 2006

This paper describes a design of low-power/small-area arithmetic circuits which are vector processing unit powering nit, divider unit and square-root unit for mobile 3D graphic accelerator. To achieve area-efficient and low-power implementation that is an essential consideration for mobile environment, the fixed-point f[mat of 16.16 is adopted instead of conventional floating-point format. The vector processing unit is designed using redundant binary(RB) arithmetic. As a result, it can operate 30% faster and obtained gate count reduction of 10%, compared to the conventional methods which consist of four multipliers and three adders. The powering nit, divider unit and square-root nit are based on logarithm number system. The binary-to-logarithm converter is designed using combinational logic based on six-region approximation method. So, the powering mit, divider unit and square-root unit reduce gate count when compared with lookup table implementation.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.3
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• pp.66-77
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• 2002

This paper deals with an implementation of the navigation parameter extraction technique using the TMS320C80 multimedia video processor (MVP). Especially, this Paper focuses on the relative position estimation algorithm which plays an important role in real-time operation of the overall system. Based on the relative position estimation algorithm using the images obtained at two locations, we develop a fast algorithm that can reduce large amount of computation time and fit into fixed-point processors. Then, the algorithm is reconfigured for parallel processing using the 4 parallel processors in the MVP. As a result, we shall demonstrate that the navigation parameter extraction system employing the MVP can operate at full-frame rate, satisfying real-time requirement of the overall system.

• The Journal of the Acoustical Society of Korea
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• v.23 no.3
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• pp.262-267
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• 2004

AMR-WB (Adaptive Multi Rate Wideband) speech codec, the most recent voice codec standardized by 3GPP, has the wider audio bandwidth of 50∼7000 Hz and operates on nine speech coding bit rates between 6.60 and 23.85 kbit/s. This Paper presents the real-time implementation of AMR-WB speech codec by using a 16 bit fixed-point TeakLite DSP. The implemented AMR-WB codec requires the complexity of 52.2 MIPS at 23.85 kbit/s mode and also needs the program memory of 17.9 kwords, data RAM of 11.8 kwords, and data ROM of 10.1kwords. It was verified through passing the all test vectors provided by 3GPP with maintaining bit exactness. Stable operations on the real-time testing board were also proved without any distortions and delays for the audio in/out.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.4
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• pp.65-71
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• 2000

Finite wordlength effect of the recursive implementation of SDFT(sliding-DFT) is analytically derived in this paper. Representation errors of the twiddle coefficients and the data registers are the two major causes of the spectral errors in the recursive implementation. The noise-to-signal ratio is analytically derived in terms of the coefficients wordlength, the data registers wordlength, and the DFT's block-length used in the computation Error dynamic equation is obtained from the recursive DFT and the probabilistic models for the coefficients error and the round-off error are introduced for the NSR derivation, The result of the NSR derivation is verified with the simulation data.

• The Journal of the Acoustical Society of Korea
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• v.24 no.1
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• pp.52-57
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• 2005

The adaptive multirate wideband (AMR-WB) speech coder has an extended audio bandwidth from 50 Hz to 7 kBz and operates on nine speech coding bit-rates from 6.6 to 23.85 kbit/s. In this Paper, we present the real-time implementation of AMR-WB speech coder using 16bit fixed-point TMS320C5509 that has dual MAC units. Firstly, We implemented AMR-WB speech coder in C 1anguage level using intrinsics, and then performed optimization in assembly language. The computational complexity of the implemented AMR-WB coder at 23.85 kbit/s is 42.9 Mclocks. And this coder needs the program memory of 15.1 kwords, data ROM of 9.2 kwords and data RAM of 13.9 kwords.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.9C
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• pp.1337-1344
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• 2004

This paper deals with analysis and real-time Implementation of a wide band adaptive multirate speech codec (AMR-WB) using a fixed-point DSP of TI's TMS320C6201. In the AMR-WB codec, input speech is divided into two frequency bands, lower and upper bands, and processed independently. The lower band signal is encoded based on the ACELP algorithm and the upper band signal is processed using the random excitation with a linear prediction synthesis filter. The implemented AMR-WB system used 218 kbytes of program memory and 92 kbytes of data memory. And its proper operation was confirmed by comparing a decoded speech signal sample-by-sample with that of PC-based simulation. Maximum required time of 5 75 ms for processing a frame of 20 ms of speech validates real-time operation of the Implemented system.

• The Journal of the Acoustical Society of Korea
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• v.21 no.7
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• pp.648-655
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• 2002

This paper describes implementation of a multi-channel G.723.1 Annex A (G.723.1A) focused on code optimization using a high performance general purpose Digital Signal Processor (DSP), To implement a multi-channel G.723.1A functional complexities of the ITU-T G.723.1A fixed-point C-code are measures an analyzed. Then we sort and optimize C functions in complexity order. In parallel with optimization, we verify the bit-exactness of the optimized code using the ITU-T test vectors. Using only internal memory, the optimized code can perform full-duplex 17 channel processing. In addition, we further increase the number of available channels per DSP into 22 using fast codebook search algorithms, referred to as bit -compatible optimization.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.1 no.2
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• pp.91-98
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• 2008

Domestic standard for Korean T-DMB includes MPEG-4 BSAC (Bit Sliced Arithmetic Coding) audio coding that has been established in 2003. This paper presents an implementation and optimization of MPEG-4 BSAC Audio Decoder on ARM926EJ-S processor. Tools and modules of the BSAC audio decoder were implemented with 32-bit fixed point operations. Further optimization was accomplished using ARM926EJ-S Inline Assembly. The optimization was based on the total number of multiplications and MAC (Multiply and Accumulation) operations causing most of core cycles of ARM926EJ-S, and also based on analysis of ARMv5 instructions. The result of optimization was evaluated on the basis of MIPS (Million Instruction per second). Implementation results show that BSAC bitstream at 96kbps can be decoded in real-time at 65MHz CPU clocks.