• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.4
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• pp.331-341
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• 1991

The discrete cosine transform (DCT) is widely used in many signal processing areas, including image and speech data compression. In this paper, we investigate a fixed-point error analysis for fast DCT algorithms, namely, Lee [6], Hou [7] and Vetterli [8]. A statistical model for fixed-point error is analyzed to predict the output noise due to the fixed-point implementation. This paper deals with two's complement fixed-point data representation with truncation and rounding. For a comparison purpose, we also investigate the direct form DCT algorithm. We also propose a suitable scaling model for the fixed-point implementation to avoid an overflow occurring in the addition operation. Computer simulation results reveal that there is a close agreement between the theoretical and the experimental results. The result shows that Vetterli's algorithm is better than the other algorithms in terms of SNR.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.33-42
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• 1997

Fixed-point optimization utility software that can aid scaling and wordlength determination of digital signal processign algorithms written in C or C$\^$++/ language is developed. This utility consists of two programs: the range estimator and the fixed-point simulator. The former estimates the ranges of floating-point variables for automatic scaling purpose, and the latter translates floating-point programs into fixed-point equivalents for evaluating te fixed-point performance by simulation. By exploiting the operator overloading characteristics of C$\^$++/ language, the range estimation and the fixed-point simulation can be conducted just by modifying the variable declaration of the original program. This utility is easily applicable to nearly all types of digital signal processing programs including non-linear, time-varying, multi-rate, and multi-dimensional signal processing algorithms. In addition, this software can be used for comparing the fixed-point characteristics of different implementation architectures.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6A
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• pp.593-602
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• 2006

This paper propose to methodology for deciding suitable bit size that minimizes hardware complexity and performance degradation from floating-point design the fixed-point implementation of downlink traffic channel of IEEE 802.16e OFDMA TDD system. One of the major considering issues for implementing fixed-point design is to select Saturation or Quantization properly with the knowledge of signal distribution by pdf or histogram. Also, through trial and error, we should execute exhaustive computer simulation for various bit sizes, hence obtain appropriate bit size while minimizing performance degradation. We carry out computer simulation to decide the optimized bit size of downlink traffic channel under AWGN and ITU-R M.1225 Veh-A channel model.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.257-258
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• 2006

In this paper, we address several issues in the real time implementation of MPEG-1 Layer II decoder on a fixed-point digital signal processor (DSP), especially TMS320C6416. There is a trade-off between processing speed and the size of program/data memory for the optimal implementation. In a view of the speed optimization, we first convert the floating point operations into fixed point ones with little degradation in audio quality, and then the look-up tables used for the inverse quantization of the audio codec are forced to be located into the internal memory of the DSP. And then, window functions and filter coefficients in the decoder are precalculated and stored as constant, which makes the decoder faster even larger memory size is required. It is shown from the real-time experiments that the fixed-point implementation enables us to make the decoder with a sampling rate of 48 kHz operate with 3 times faster than real-time on TMS320C6416 at a clock rate of 600 MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.3C
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• pp.240-246
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• 2008

An MPEG-2/4 AAC decoder on 16-bit fixed-point processor is presented in this paper. To meet audio quality criteria, despite small word length, special design methods for 16-bit foxed-point AAC decoder were devised. This paper presents particular algorithms for 16-bit AAC decoding. We have implemented an efficient AAC decoder using the proposed algorithms. Audio contents can be replayed in the decoder without quality degradation.

• Speech Sciences
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• v.10 no.2
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• pp.65-75
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• 2003

This paper describes the issues associated with the real-time implementation of G.723.1A dual-rate speech coder on a TMS320VC5402 DSP. Firstly, the main features of the G.723.1A speech coder and the procedure involved in the implementation using assembly and C languages are discussed. Various real-time implementation issues such as memory/MIPS tradeoffs are also presented. For fixed-point implementation, we converted the ITU-T fixed-point ANSI C code into TMS320VC5402 code in the bit-exact way through verification using the test vectors. Finally, as the result of implementation, we present the MIPS and memory requirement for the real-time operation.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.651-654
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• 1999

This paper investigates the varying characteristics of the performance degradation resulting from the different combination of wordlength in fixed-point implementation of recursive sinusoidal transform. The performance degradation is analytically derived in the form of noise-to-signal power ratio. The best wordlength combination is shown to be the equal length distribution of the given number of bits between the transform coefficients and the data. The analysis results are also verified through the computer simulations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1195-1201
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• 2005

This paper deals with procedures and results for teal time implementation of G.729 speech coder and channel coder including convolution codec, viterbi decoder, and interleaver using a fixed point DSP chip for radio communication systems. We described the method for real-time implementation based on integer simulation results and explained the implemented results by quality performance and required complexity for real-time operation. The required complexity was 24MIPS and 9MIPS in computational load, and 12K words and 4K words in execution code length for speech and channel. The functional evaluation was performed into two steps. The one was bit exact comparison with a fixed point C code, the other was executed by actual speech samples and error test vectors. Unlik other results such as individual implementation, We implemented speech and channel coders on a DSP chip with 160MIPS computation capability and 64 K words memory on chip. This results outweigh the conventional methods in the point of system complexity and implementation cost for radio communication system.

• Journal of IKEEE
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• v.22 no.3
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• pp.805-809
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• 2018

In this paper, we analyze the change of accuracy when fixed point arithmetic is used instead of floating point arithmetic in binary weight network(BWN). We observed the change of accuracy by varying total bit size and fraction bit size. If the integer part is not changed after fixed point approximation, there is no significant decrease in accuracy compared to the floating-point operation. When overflow occurs in the integer part, the approximation to the maximum or minimum of the fixed point representation minimizes the decrease in accuracy. The results of this paper can be applied to the minimization of memory and hardware resource requirement in the implementation of FPGA-based BWN accelerator.

• Journal of Institute of Control, Robotics and Systems
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• v.13 no.12
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• pp.1160-1166
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• 2007

This paper presents the design and implementation of an embedded image stabilization control system for a mobile phone with a built-in camera. Image stabilization is a family of techniques for reducing image blur resulting from minute camera shake due to hand-held shooting, thereby allowing the use of shutter speeds slower than values normally required to obtain sharp images. A mechanical image stabilizer mechanism developed for a camera mobile phone is introduced and a digital control system as a part of the image stabilization system is designed and implemented on an 8-bit microcontroller with integer arithmetic in C. This paper focuses primarily on issues that need to be taken into consideration for fixed-point implementation of the digital controller. Several experimental results are presented to demonstrate the performance of the implemented image stabilization control system.