• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.935-938
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• 2003

The performance of elliptic curve based on public key cryptosystems is mainly appointed by the efficiency of the underlying finite field arithmetic. This work describes a finite field multiplier and divider which is implemented using SystemC. Also this present an efficient hardware for performing the elliptic curve point multiplication using the polynomial basis representation. In order to improve the speed of the multiplier with as a little extra hardware as possible, adopted hybrid finite field multiplication and finite field divider.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.35-42
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• 2007

The finite-field division can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field division takes much time to compute. In this paper, we propose a radix-4 systolic divider on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed divide, is mathematically developed and new counter structure is proposed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for YLSI design. Compared to the bit-parallel, bit-serial and digit-serial dividers, the proposed divider has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field divider using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.109-114
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• 2004

This paper presents a high-speed bit-parallel systolic divider for computing modular division A($\chi$)/B($\chi$) mod G($\chi$) in finite fields GF$(2^m)$. The presented divider is based on the binary GCD algorithm and verified through FPGA implementation. The proposed architecture produces division results at a rate of one every 1 clock cycles after an initial delay of 5m-2. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. In addition, since the proposed architecture does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and Scalability with respect to the field size m. Therefore, the proposed divider is well suited to VLSI implementation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.633-637
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• 2005

In this contribution, we developed and improved an existing GF (Galois field) dividing algorithm by suggesting a novel architecture for a finite field divider, which is frequently required for the error correction applications and the security-related applications such as the Reed-Solomon code, elliptic curve encryption/ decryption, is proposed. We utilized the VHDL language to verify the design methodology, and implemented the architecture on an FPGA chip. We suggested the n-bit lookup table method to obtain the throughput of 2m/n cycles, where m is the order of the division polynomial and n is the number of the most significant lookup-bits. By doing this, we extracted the advantages in achieving both high-throughput and less cost of the gate areaon the chip. A pilot FPGA chip was implemented with the case of m=4, n=2. We successfully utilized the Altera's EP20K30ETC144-1 to exhibit the maximum operating clock frequency of 77 MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5C
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• pp.726-736
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• 2004

In this paper, we proposed a new scalar multiplier structure needed for an elliptic curve cryptosystem(ECC) over the standard basis in GF(2$^{163}$ ). It consists of a bit-serial multiplier and a divider with control logics, and the divider consumes most of the processing time. To speed up the division processing, we developed a new division algorithm based on the extended Euclid algorithm. Dynamic data dependency of the Euclid algorithm has been transformed to static and fixed data flow by a localization technique, to make it independent of the input and field polynomial. Compared to other existing scalar multipliers, the new scalar multiplier requires smaller gate counts with improved processor performance. It has been synthesized using Samsung 0.18 um CMOS technology, and the maximum operating frequency is estimated 250 MHz. The resulting performance is 148 kbps, that is, it takes 1.1 msec to process a 163-bit data frame. We assure that this performance is enough to be used for digital signature, encryption/decryption, and key exchanges in real time environments.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11a
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• pp.64-66
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• 2005

본 논문에서는 GF($2^m$) 상에서 나눗셈 연산을 위한 고속 알고리듬을 제안하고, 제안한 알고리듬을 기본으로 한 나눗셈 연산기의 하드웨어 설계 및 구현에 관하여 기술한다. 나눗셈을 위한 모듈러 연산은 개선된 이진 확장 유클리드 알고리듬 (Binary Extended Euclidian algorithm) 을 기본으로 하고 있다 성능비교 결과로부터 제안한 방법은 기존 방법에 비해 지연시간이 약 $26.7\%$ 정도 개선됨을 확인하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.925-927
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• 2011

본 논문에서는 확장 이진 최대공약수 알고리듬 (Extended Binary GCD algorithm)을 기본으로 GF($2^m$) 상에서 유한체 나눗셈 연산을 위한 고속 알고리듬을 제안하고, 제안한 알고리듬을 기본으로 한 나눗셈 연산기의 FPGA 설계 구현에 관하여 기술한다. 제안한 알고리듬은 Verilog HDL 로 기술하였고, Xilinx FPGA virtex4-xc4vlx15 디바이스를 타겟으로 하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.7
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• pp.1267-1275
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• 2017

This paper describes a design of cryptographic processor supporting 233-bit elliptic curves over binary field defined by NIST. Scalar point multiplication that is core arithmetic in elliptic curve cryptography(ECC) was implemented by adopting modified Montgomery ladder algorithm, making it robust against simple power analysis attack. Point addition and point doubling operations on elliptic curve were implemented by finite field multiplication, squaring, and division operations over $GF(2^{233})$, which is based on affine coordinates. Finite field multiplier and divider were implemented by applying shift-and-add algorithm and extended Euclidean algorithm, respectively, resulting in reduced gate counts. The ECC processor was verified by FPGA implementation using Virtex5 device. The ECC processor synthesized using a 0.18 um CMOS cell library occupies 49,271 gate equivalents (GEs), and the estimated maximum clock frequency is 345 MHz. One scalar point multiplication takes 490,699 clock cycles, and the computation time is 1.4 msec at the maximum clock frequency.

• Korea-Australia Rheology Journal
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• v.17 no.2
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• pp.47-62
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• 2005

The present study deals with a mathematical model describing the dynamic response of heat and mass transfer in blood flow through bifurcated arteries under stenotic condition. The geometry of the bifurcated arterial segment possessing constrictions in both the parent and the daughter arterial lumen frequently appearing in the diseased arteries causing malfunction of the cardiovascular system, is formulated mathematically with the introduction of the suitable curvatures at the lateral junction and the flow divider. The blood flowing through the artery is treated to be Newtonian. The nonlinear unsteady flow phenomena is governed by the Navier-Stokes equations while those of heat and mass transfer are controlled by the heat conduction and the convection-diffusion equations respectively. All these equations together with the appropriate boundary conditions describing the present biomechanical problem following the radial coordinate transformation are solved numerically by adopting finite difference technique. The respective profiles of the flow field, the temperature and the concentration and their distributions as well are obtained. The influences of the stenosis, the arterial wall motion and the unsteady behaviour of the system in terms of the heat and mass transfer on the blood stream in the entire arterial segment are high­lighted through several plots presented at the end of the paper in order to illustrate the applicability of the present model under study.

• The KIPS Transactions:PartA
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• v.12A no.3 s.93
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• pp.235-242
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• 2005

In this paper, we propose a new division circuit for $GF(2^m)$ applications. The proposed division circuit is based on a modified the binary GCD algorithm and produce division results at a rate of one per 2m-1 clock cycles. Analysis shows that the proposed circuit gives $47\%$ and $20\%$ improvements in terms of speed and hardware respectively. In addition, since the proposed circuit does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and scalability with respect to the field size m. Thus, the proposed divider. is well suited to low-area $GF(2^m)$ applications.