• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.45-54
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• 2020

Recently, market demands of miniaturization, high interconnection density, and fine pitch of PCBs continuously keep increasing. Therefore, SLP (substrate like PCB) technology using a modified semi additive process (MSAP) has attracted great attention. In particular, SLP technology is essential for the development of high-capacity batteries and 5G technology for smartphones. In this study, the reliability of the microvia of hybrid SLP, which is made of conventional HDI (high density interconnect) and MSAP technologies, was investigated by experimental and numerical analysis. Through thermal cycling reliability test using IST (interconnect stress test) and finite element numerical analysis, the effects of various parameters such as prepreg properties, thickness, number of layers, microvia size, and misalignment on microvia reliability were investigated for optimal design of SLP. As thermal expansion coefficient (CTE) of prepreg decreased, the reliability of microvia increased. The thinner the prepreg thickness, the higher the reliability. Increasing the size of the microvia hole and the pad will alleviate stress and improve reliability. On the other hand, as the number of prepreg layers increased, the reliability of microvia decreased. Also, the larger the misalignment, the lower the reliability. In particular, among these parameters, CTE of prepreg material has the greatest impact on the microvia reliability. The results of numerical stress analysis were in good agreement with the experimental results. As the stress of the microvia decreased, the reliability of the microvia increased. These experimental and numerical results will provide a useful guideline for design and fabrication of SLP substrate.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.3
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• pp.27-33
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• 2008

With increasing use of portable appliances such as PDA and cellular phone, changing environment of applications requires higher solder joint reliability. The ENIG (Electroless Nickel Immersion Gold) process has been widely used for fine pitch SMT (Surface Mount Technology) and BGA (Ball Grid Array) packaged devices due to its benefits including excellent solderability, high uniformity and substantial legibility throughout the packaging process. Its brittle fracture of solder, however, has received increasingly attentions. It was Down that fracture brittleness is mainly related with black pad resulting from galvanic nickel corrosion and P-enriched layer formation between the IMC (Intermetallic Compounds) and electroless nickel layer. Theoretically, smooth electroless Ni layer was blown to have a advantages in minimizing the black pad phenomenon by uniform solution exchange during immersion gold plating. Nevertheless, how to control the surface morphology of electroless Ni layer has been hardly blown. This study investigates an effect of surface morphology of Cu underlayer on surface morphology of electroless Ni layer. To obtain various kinds of surface morphology of Cu layer, two types of Cu etching chemical and a number of Cu etching treatment were applied.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.4
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• pp.7-15
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• 2000

The purpose of this work is to evaluate the solderahility and characteristics of solder joints. Bridge defect of solder joint was examined in natural atmosphere and $N_2$ condition. Consequently, wettability was excellent for each of Sn-Pb plated Cu specimen, Sn plated Cu specimen, and Cu polished in $N_2$ condition. The wetting time in $N_2$ condition was shorter than that of natural atmosphere condition, showing the decreasing values of about 0.2~0.45 seconds. The max. wetting force under the $N_2$ condition was more increasing that of natural atmosphere condition, showing the increasing values of about 1.8~2.8 N. With the result of wetting balance test, the wetting time ($t_2$) and wetting farce according to increasing amount of $N_2$ from 10 1/min to 30 1/min, the wetting time ($t_2$) was reduced about 0.25 second and wetting force was increased about 2.3 N. In non-cleaning flux, when $N_2$ gas is applied, it is compensated to decrease of wettability. In the case of using the $N_2$ gas, the wettability was improved. The reason for improving wettability is due to preventing the formation of dross. The generation rate of bridge in $N_2$ condition decreased than that of natural atmosphere, and when the specimen had a fine pitch, the rate of bridge defects was considerably decreased in $N_2$ condition, showing the decreasing rate of 25~75%.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.12
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• pp.1120-1127
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• 2013

In this paper, novel chip-on-chip(CoC) flip-chip bump structures using chip-on-wafer(CoW) process technology are proposed, designed and fabricated, and their microwave frequency responses are analyzed. With conventional bumps of Cu pillar/SnAg and Cu pillar/Ni/SnAg and novel Polybenzoxazole(PBO)-passivated bumps of Cu pillar/SnAg, Cu pillar/Ni/SnAg and SnAg with the deposition option of $2^{nd}$ Polyimide(PI2) layer on the wafer, 10 kinds of CoC samples are designed and their frequency responses up to 20 GHz are investigated. The measurement results show that the bumps on the wafers with PI2 layers are better for the batch flip-chip process and have average insertion loss of 0.14 dB at 18 GHz. The developed bump structures for chips with fine-pitch pads show similar or slightly better insertion loss of 0.11~0.14 dB up to 18 GHz, compared with that of 0.13~0.17 dB of conventional bump structures in this study, and we find that they could be utilized in various microwave packages for high integration density.

• Journal of Sasang Constitutional Medicine
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• v.19 no.3
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• pp.126-143
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• 2007

1. Objectives The purpose of this study is to find out the grade of practical use, the important element and the significant characteristics of Sasangin' s face, voice, skin and pulse diagnostic impression, in Sasang constitutional clinical diagnosis. 2. Methods We analysed the survey data about Sasangin' s face, voice, skin and pulse diagnostic impression, drawn up by specialist in Sasang constitutional medicine. 3. Results and Conclusions (1) In the application degree of face feature, the case which it was applied with 20-40% and 40-60% were 16 people(43.2%) respectively. In voice, the case applied with 0-20% was 19 people(51.4%), in skin, 0-20% and 20-40% were 14 people(37.8%) respectively and in pulse diagnosis, 0-20% were 25 people(73.0%). (2) In constitutional diagnosis, the important element of face were 'frontal whole shape', 'whole impression' and 'size and shape of eye, ear, mose and mouth', the important element of voice 'speed of speech', 'purity and impurity' and 'pitch', the important element of skin 'thickness', 'feel of touch' and 'size of skin pores' and the important element of pulse diagnosis 'speed of pulse', 'sinking and floating' and 'weakness and firmness'. (3) The important face characteristics of Taeyangin were 'bright eye', 'broad forehead' and 'strong impression', Soyangin 'protruding forehead', 'thin and small lips', 'narrowing and sharp chin', Taeumin 'thick lips', 'flat face', 'large eye, nose, ear and mouth' and Soeumin 'long and slender face', 'downward slanting eyes' and 'small eye, nose, ear and mouth', The important voice characteristics of Taeyangin were 'loud' and 'clear', Soyangin 'rapid' and 'high-pitched tone', Taeumin 'chick', 'slow' and 'low-pitched tone' and Soeumin 'small and feeble' and 'slow'. The important skin characteristics of Taeyangin were 'thin' and 'white', Soyangin 'thin', 'smooth' and 'elastic', Taeumin 'thick', 'large skin-pore', 'coarse' and Soeumin 'soft', 'thin' and 'subtle skin-pore'. The important pulse characteristics of Taeyangin were 'rapid' and 'large', Soyangin 'rapid' and 'floating', Taeumin 'tense', 'long' and 'solid' and Soeumin 'fine', 'weak' and 'slow'.

• The Journal of the Acoustical Society of Korea
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• v.20 no.3
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• pp.24-33
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• 2001

this paper describes a baseline for an implementation of a corpus-based Korean TTS system. The conventional TTS systems using small-sized speech still generate machine-like synthetic speech. To overcome this problem we introduce the corpus-based TTS system which enables to generate natural synthetic speech without prosodic modifications. The corpus should be composed of a natural prosody of source speech and multiple instances of synthesis units. To make a phone level synthesis unit, we train a speech recognizer with the target speech, and then perform an automatic phoneme segmentation. We also detect the fine pitch period using Laryngo graph signals, which is used for prosodic feature extraction. For break strength allocation, 4 levels of break indices are decided as pause length and also attached to phones to reflect prosodic variations in phrase boundaries. To predict the break strength on texts, we utilize the statistical information of POS (Part-of-Speech) sequences. The best triphone sequences are selected by Viterbi search considering the minimization of accumulative Euclidean distance of concatenating distortion. To get high quality synthesis speech applicable to commercial purpose, we introduce a domain specific database. By adding domain specific database to general domain database, we can greatly improve the quality of synthetic speech on specific domain. From the subjective evaluation, the new Korean corpus-based TTS system shows better naturalness than the conventional demisyllable-based one.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2012.11a
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• pp.123-123
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• 2012

최근 연구되고 있는 TSV(Through Silicon Via) 기술은 Si 웨이퍼 상에 직접 전기적 연결 통로인 관통홀을 형성하는 방법으로 칩간 연결거리를 최소화 할 수 있으며, 부피의 감소, 연결부 단축에 따른 빠른 신호 전달을 가능하게 한다. 이러한 TSV 기술은 최근의 초경량화와 고집적화로 대표되는 전자제품의 요구를 만족시킬 수 있는 차세대 실장법으로 기대를 모으고 있다. 한편, 납땜 재료의 주 원료인 주석은 주로 반도체 소자의 제조, 반도체 칩과 기판의 접합 및 플립 칩 (Flip Chip) 제조시의 범프 형성 등 반도체용 배선재료에 널리 사용되고 있다. 최근에는 납의 유해성 때문에 대부분의 전자제품은 무연솔더를 이용하여 제조되고 있지만, 주석을 이용한 반도체 소자가 고밀도화, 고 용량화 및 미세피치(Fine Pitch)화 되고 있기 때문에, 반도체 칩의 근방에 배치된 주석으로부터 많은 알파 방사선이 방출되어 메모리 셀의 정보를 유실시키는 소프트 에러 (Soft Error)가 발생되는 위험이 많아지고 있다. 이로 인해, 반도체 소자 및 납땜 재료의 주 원료인 주석의 고순도화가 요구되고 있으며, 특히 알파 방사선의 방출이 낮은 로우알파솔더 (Low Alpha Solder)가 요구되고 있다. 이에 따라 본 연구는 4인치 실리콘 웨이퍼상에 직경 $60{\mu}m$, 깊이 $120{\mu}m$의 비아홀을 형성하고, 비아 홀 내에 기능 박막증착 및 전해도금을 이용하여 전도성 물질인 Cu를 충전한 후 직경 $80{\mu}m$의 로우알파 Sn-1.0Ag-0.5Cu 솔더를 접합 한 후, 접합부 신뢰성 평가를 수행을 위해 고속 전단시험을 실시하였다. 비아 홀 내 미세구조와 범프의 형상 및 전단시험 후 파괴모드의 분석은 FE-SEM (Field Emission Scanning Electron Microscope)을 이용하여 관찰하였다. 연구 결과 비아의 입구 막힘이나 보이드(Void)와 같은 결함 없이 Cu를 충전하였으며, 고속전단의 경우는 전단 속도가 증가할수록 취성파괴가 증가하는 경향을 보였다. 본 연구를 통하여 전해도금을 이용한 비아 홀 내 Cu의 고속 충전 및 로우알파 솔더 볼의 범프 형성이 가능하였으며, 이로 인한 전자제품의 소프트에러의 감소가 기대된다.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.3
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• pp.55-62
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• 2001

With a spread of BGA, CSP and fine pitch devices, the need of flatter surface finish in bare board is becoming more critical in solderability. The electroless Ni/Au plating has a solution of these needs and also has being spread to apply to surface finish for bare board in many electronic goods. But, the electroless Ni/Au plating had several issues such as Ni oxidation and phosphorous contents. Before this study, we studied on the effect of BGA solderability in electroless Ni/Au plating and chose some major factors such as the oxidation property of NiP plating and warpage of board. Firstly, we made test board with various plating conditions and improved the plating property through the improvement of NiP oxidation reducing P content. Also, we minimized the warpage of board with the improvement of inner layer structure and the analysis of warpage. For the evaluation of solderability, we analyzed the warpage of board and the plating property after mounting BGA on the board with optimizing conditions. The solder joint of BGA is investigated by SEM(Scanning Electronic Microscope) and OM(Optical Microscope). The composition of joint is used by EDS(Energy Dispersive Spectroscopy). We analyzed the fracture strength and mode by ball shear teser.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.2
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• pp.37-43
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• 1999

Modules of the system that requires large capacity and high-speed information processing are implemented in the form of MCM that allows high-speed data processing, high density circuit integration and widely applied to such fields as ATM, GPS and PCS. Hence we developed the ATM switching module that is consisted of three chips and 2.48 Gbps data throughput, in the form of 10 multi-layer by Cu/Photo-BCB and 491pin PBGA which size is $48 \times 48 \textrm {mm}^2$. hnologies required for the development of the MCM includes extracting parameters for designing the substrate/package through the interconnect characterization to implement the high-speed characteristics, thermal management at the high-density MCM, and the generation of the testability that is one of the most difficult issues for developing the MCM. For the development of the ATM Switching MCM, we extracted signaling delay, via characteristics and crosstalk parameters through the interconnect characterization on the MCM-D. For the thermal management of 15.6 Watt under the high-density structure, we carried out the thermal analysis. formed 1.108 thermal vias through the substrate, and performed heat-proofing processing for the entire package so that it can keep the temperature less than $85^{\circ}C$. Lastly, in order to ensure the testability, we verified the substrate through fine pitch probing and applied the Boundary Scan Test (BST) for verifying the complex packaging/assembling processes, through which we developed an efficient and cost-effective product.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.67-73
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• 2009

Compared to the chip-bonding process utilizing solder bumps, flip chip process using Cu pillar bumps can accomplish fine-pitch interconnection without compromising stand-off height. Cu pillar bump technology is one of the most promising chip-mounting process for RF packages where large gap between a chip and a substrate is required in order to suppress the parasitic capacitance. In this study, Cu pillar bumps and Sn bumps were electroplated on a chip and a substrate, respectively, and were flip-chip bonded together. Contact resistance and chip shear force of the Cu pillar bump joints were measured with variation of the electroplated Sn-bump height. With increasing the Sn-bump height from 5 ${\mu}m$ to 30 ${\mu}m$, the contact resistance was improved from 31.7 $m{\Omega}$ to 13.8 $m{\Omega}$ and the chip shear force increased from 3.8 N to 6.8 N. On the contrary, the aspect ratio of the Cu pillar bump joint decreased from 1.3 to 0.9. Based on the variation behaviors of the contact resistance, the chip shear force, and the aspect ratio, the optimum height of the electroplated Sn bump could be thought as 20 ${\mu}m$.