• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2009.05a
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• pp.110-110
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• 2009

최근 차세대 비휘발성 메모리(NVM) 기술은 메모리의 성능과 기존의 한계점을 효과적으로 극복하며 활발한 연구를 통해 비약적으로 발전하고 있으며 특히, phase-change random access memory (PRAM)은 ferroelectric random access memory (FeRAM)과 magneto-resistive random access memory (MRAM)과 같은 다른 NVM 소자와 비교하여 기존의 DRAM과 구조적으로 비슷하고 상용화가 빠르게 진행될 수 있을 것으로 예상되는 바, PRAM에 사용되는 상변화 물질의 식각을 수행하고 X-ray photoelectron spectroscopy (XPS)를 통해 표면의 열화현상을 관찰하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.1
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• pp.88-92
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• 2023

The ferroelectricity in Hf_0.5Zr_0.5O₂ (HZO) thin films is one of the most interesting topics for next-generation nonvolatile memory applications. It is known that a crystallization process is required at a temperature of 400℃ or higher to form an orthorhombic phase that results in the ferroelectric properties of the HZO film. However, to realize the integration of ferroelectric HZO films in the back-end-of-line, it is necessary to reduce the annealing temperature below 400℃. This study aims to comprehensively analyze the ferroelectric properties according to the annealing temperature (350-500℃) and time (1-5 h) using a furnace as a crystallization method for HZO films. As a result, the ferroelectric behaviors of the HZO films were achieved at a temperature of 400℃ or higher regardless of the annealing time. At the annealing temperature of 350℃, the ferroelectric properties appeared only when the annealing time was sufficiently increased (4 h or more). Based on these results, it was experimentally confirmed that the optimization of the annealing temperature and time is very important for the ferroelectric phase crystallization of HZO films and the improvement of their ferroelectric properties.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.1 s.34
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• pp.21-26
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• 2005

The field effect transistors (FETs) were fabricated ell $Y_2O_3/Si(100)$ substrates by the conventional memory processes and sol-gel process using $(Bi,La)Ti_3O_{12}(BLT)$ ferroelectric gate materials. The remnant polarization ($2Pr = Pr^+-Pr^-$) int Pt/BLT/Pt/Si capacitors increased from $22 {\mu}C/cm^2$ to $30{\mu}C/ cm^2$ at 5V as the annealing temperature increased from $700^{\circ}C$ to $750^{\circ}C$. There was no drastic degradation in the polarization values after applying the retention read pulse for $10^{5.5}$ seconds. The capacitance-voltage data of $Pt/BLT/Y_2O_3/Si$ capacitors at 5V input voltage showed that the memory window voltage decreased from 1.4V to 0.6V as the annealing temperature increased from $700^{\circ}C$ to $750^{\circ}C$. The leakage current of the $Pt/BLT/Y_2O_3/Si$ capacitors annealed at $750^{\circ}C$ was about $510^{-8}A/cm^2$ at 5V. From the drain currents versus gate voltages ($V_G$) for $Pt/BLT/Y_2O_3/Si(100)$ FET devices, the memory window voltages increased from 0.3V to 0.8V with increasing tile $V_G$ from 3V to 5V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.10 s.340
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• pp.1-8
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• 2005

In this paper, a FRAM design style based on PMOS-gating cell structure is described. The memory cell consists of a PMOS access transistor and a ferroelectric capacitor. Its plate is grounded. The proposed scheme employs three novel operating methods: 1) $V_{DD}$ precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore, Because this configuration doesn`t need the on-pitch plate control circuitry, it is effective in realizing cost-effective chip sizes. Implementation for a 2.5-V, 1-Mb FRAM prototype design in a $0.25-{\mu}m$, triple-well technology shows a chip size of $3.22\;mm^{2}$, an access time of 48 ns and an active current of 11 mA. The cell efficiency is 62.52 $\%$. It has gained approximately $20\;\%$ improvement in the cell array efficiency over the conventional plate-driven FRAM scheme.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.35-35
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• 2003

Recent progress in the integration of the ferroelectric random access memories (FRAM) has attracted much interest. Strontium bismuth tantalate(SBT) is one of the most attractive materials for use in nonvolatile-memory applications due to low-voltage operations, low leakage current, and its excellent fatigue-free property. High-density FRAMs operated at a low voltage below 1.5V are applicable to mobile devices operated by battery. SBT films thinner than 0.1 #m can be operated at a low voltage, because the coercive voltage (Vc) decreases as the film thickness is reduced. In addition, the thickness of the SBT film will have to be reduced so it can fit between adjacent storage nodes in a pedestal type capacitor in future FRAMs.

• Journal of the Korean Ceramic Society
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• v.31 no.10
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• pp.1115-1122
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• 1994

ZT/PZT/ZT multi-layered thin films were deposited on silicon substrate by co-sputtering method for FEMFET device application. Effects of Pb/(Zr+Ti) ratio, films thickness, annealing conditions and substrate temperature on the ferroelectric behavior of the multi-layered films were studied. The best memory device characteristics with leakage current of 2$\times$10-8 A/$\textrm{cm}^2$ and breakdown field of about 1 MV/cm could be obtained with ZT(250 $\AA$) / PZT(1000 $\AA$)/ZT(750 $\AA$) multi-layered thin film deposited at 35$0^{\circ}C$ and post-annealed at $700^{\circ}C$ for 120 sec by RTA(Rapid Thermal Annealing).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.341-344
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• 2001

We investigate the electronic structure of perovskite PbTiO$_3$ and the microscopic origin of the ferroelectric lattice instability through first-principles pseudopotential calculations. We examine pseudo Jahn-Teller effect to discuss the lattice instability. The JT effect is caused by the hybridization of the p-orbitals of O atoms and d-orbital of Ti atom. We find the JT effect is most significant at Brillouin zone renter.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.39-40
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• 2005

Ferroelectric Eu-substituted $Bi_4Ti_3O_{12}$ (BET) thin films with a thickness of 200 nm were deposited on Pt(111)/Ti/SiO$_2$/Si(100) substrate by means of the liquid delivery MOCVD system and annealed at several temperatures in an oxygen atmosphere. At annealing temperature above $600^{\circ}C$, the microstructure of layered perovskite phase was observed. The remanent polarization of these films increased with increase in annealing temperature. The remanent polarization values ($2P_r$) of the BET thin films annealed at $720^{\circ}C$ were $37.71{\mu}C/cm^2$ at an applied voltage of 5 V.

• Journal of the Korean Vacuum Society
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• v.11 no.2
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• pp.103-107
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• 2002

Metal/ferroelectric/semiconductor field effect transistors(MFSFET′s) with various gate electrodes, that are aluminum, platinum and poly-Si, using rapid thermal annealed $LiNbO_3$/Si(100) structures were fabricated and the properties of the FET′s have been discussed. The drain current of the "on" state of FET with Pt electrode was more than 3 orders of magnitude larger than the "off" state current at the same "read" gate voltage of 1.5 V, which means the memory operation of the MFSFET. A write voltage as low as about $\pm$4 V, which is applicable to low power integrated circuits, was used for polarization reversal. The retention properties of the FET using Al electrode were quite good up to about $10^3$ s and using Pt electrode remained almost the same value of its initial value over 2 days at room temperature.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.103-104
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• 2006

$Pb(Zr,Ti)O_3(PZT)$ is very attractive ferroelectric materials for ferroelectric random access memory (FeRAM) applications because of its high polarization ability and low process temperature. However, Chemical Mechanical Polishing (CMP) pressure and velocity must be carefully adjusted because FeRAM shrinks to high density devices. The contaminations such as slurry residues due to the absence of the exclusive cleaning chemicals are enough to influence on the degradation of PZT thin film capacitors. The surface characteristics of PZT thin film were investigated by the change of process parameters and the cleaning process. Both the low CMP pressure and the cleaning process must be employed, even if the removal rate and the yield were decreased, to reduce the fatigue of PZT thin film capacitors fabricated by damascene process. Like this, fatigue characteristics were partially controlled by the regulation of the CMP process parameters in PZT damascene process. And the exclusive cleaning chemicals for PZT thin films were developed in this work.