• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.4
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• pp.9-17
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• 2012

In this paper, we show the memory effect of the high-power amplifiers for wied-band signals, present a compensation method for the nonlinearity combined with memory effect, and analyze its performance. For the modeling and the compensation of the nonlinear high-power amplifier with memory effect, we investigate the Volterra series model, the Wiener model, and the Hammerstein model. As a compensator scheme, we propose a digital feedforward technique. Compared to analog feed-forward scheme, the proposed scheme has better stability and adaptability to the environmental changes. It has a simpler structure than the conventional digital nonlinear compensation schemes. The result of computer simulations using ADS of the Agilent shows that spectral re-growth is suppressed by more than 20 dB, which amounts to at least 10 dB back-off. Considering the compensation performance, implementation complexity, and convergence rate, we could conclude the Wiener model is most suitable for the proposed scheme.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.9
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• pp.6-12
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• 1999

It is difficult to realize adaptive main carrier rejection circuit in feedforward-type LPA(Linear Power Amplifier) because the gain and nonlinear characteristics of power amplifier are changed according to operating frequency, voltage, temperature. Usually, pilot tones are used for adaptive LPA operation. but in this paper, the relative phase, which in obtained through I&Q demodulator using input signals as LO signals and main-path & sub-path signals as RF signals, and the magnitude of main-path & sub-path signals are compared, so main carrier rejection is obtained. The proposed method rejects main carriers by 28.34 ~ 34.66dB (@Po=36.2 ~ 28.2 dBm/tone) with two tones at 877MHz, 882MHz and also rejects main carriers by 31.3dB despite changing condition of operating voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.10
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• pp.1143-1153
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• 2010

In this paper, we propose an alternative method to increase the distortion cancellation bandwidth of an analog RF feedback power amplifier by using a negative group delay circuit(NGDC). A limited distortion cancellation bandwidth due to the group delay(GD) mismatch discouraged the use of feedback technique in spite of its powerful linearization performance. With the fabricated NGDC with positive phase slope over frequency, the feedback amplifier of the proposed topology experimentally achieved adjacent channel leakage ratio(ACLR) improvement of 15 dB over 50 MHz bandwidth at wideband code division multiple access(WCDMA) downlink band when tested with 2-carrier WCDMA signal. At an average output power of 28 dBm, ACLR of 25.1 dB is improved to obtain -53.2 dBc at 5 MHz offset.

• 한국정보통신설비학회:학술대회논문집
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• 2003.08a
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• pp.296-299
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• 2003

본 논문은 IMT-2000 대역에서 동작하는 피드포워드 증폭기의 선형성 개선을 위한 각 증폭기의 이득 평탄도의 영향에 관한 것이다. 피드포워드 증폭기의 동작 특성을 조사하기 위하여 WCDMA 신호를 인가하여 최종 출력 10W에서 성능을 측정하였다. 특히, 피드포워드 증폭기의 선형성 개선에 영향을 미치는 원인 중, 각 증폭기의 이득 평탄도의 변화에 따르는 선형성의 개선 양에 대하여 조사하였다. 전력 증폭기는 40MHz, 오차 증폭기는 40MHz와 80MHz의 대역에서 이득 평탄도를 변화시키면서 선형성의 개선 양을 조사하였으며, 오프셋 5MHz 지점에서 IMSR을 측정하였다. 측정 결과. 20dB 이상의 개선 효과를 나타내기 위해서는 전력 증폭기는 1.5dB 이내, 오차 증폭기는 0.5dB 이내의 이득 평탄도를 가져야 함을 확인하였으며, 오차 증폭기의 이득 평탄도가 선형성 개선에 더 큰 영향을 미침을 확인하였다.

• Journal of IKEEE
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• v.20 no.3
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• pp.318-321
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• 2016

As IoT industry are growing fast, The importance of power management system is also being magnified. CMOS High power-supply rejection ratio(PSRR) Low-dropout(LDO) regulator is achieved by the proposed ripple Subtractor, Feed-forward capacitor and OTA in this paper. The LDO is implemented in $0.18-{\mu}m$ CMOS technology. With the proposed structures, in the maximum loading of 40mA, Simulation result achieves PSRR of -73.4dB at 500kHz and PSRR better than -40dB when frequency is below 10MHz with $6.8-{\mu}F$ output capacitor.

• Proceedings of the KIPE Conference
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• 2018.11a
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• pp.95-97
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• 2018

The power quality of Single Phase Grid-Connected Inverters (GCIs) has received much attention with the increasing number of Distributed Generation (DG) systems. However, the performance of single phase GCIs get degraded due to several factors such as the grid voltage harmonics, the dead time effect, and the turn ON/OFF of the switches, which causes the harmonics at the output of GCIs. Therefore, it is not easy to satisfy the harmonic standards such as IEEE 519 and P1547 without the help of harmonic compensator. To meet the harmonic standards a certain kind of harmonic controller needs to be added to the current control loop to effectively mitigate the low order harmonics. In this paper, the harmonic compensation is performed using a novel robust harmonic compensation method based on Digital Lock-in Amplifier (DLA). In the proposed technique, DLAs are used to extract the amplitude and phase information of the harmonics from the output current and compensate it by using a simple PI controller in the feedforward manner. In order to show the superior performance of the proposed harmonic compensation technique, it is compared with those of conventional harmonic compensation methods in terms of the effectiveness of harmonic elimination, complexity, and implementation. The validity of the proposed harmonic compensation techniques for the single phase GCIs is verified through the experimental results with a 5kW single phase GCI. Index Terms -Single Phase Grid Connected Inverter (SPGCI), Harmonic Compensation Method, Total Harmonic Distortion (THD) and Harmonic Standard.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.3
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• pp.184-196
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for precision measurement of current flowing through a secondary cell battery in a battery management system (BMS). The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design. In addition, the ±30mV input voltage is resolved by the ADC with 15-bit resolution, eliminating the need for an additional programmable gain amplifier (PGA). The proposed a single-bit 2nd-order delta-sigma modulator has been implemented in a 350-nm CMOS process. It achieves 95.46-dB signal-to-noise-and-distortion ratio (SNDR), 96.01-dB spurious-free dynamic range (SFDR), and 15.56-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 400 for 5-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 670×490 ㎛2 and 414 ㎼, respectively.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.5
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• pp.831-835
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• 2016

In this paper, a dual-channel feed-forward transimpedance(TIA) array is realized in a standard $0.18-{\mu}m$ CMOS technology which exploits automatic gain control function to provide 40-dB input dynamic range for either detecting targets nearby or sensing imminent danger situations. Compared to the previously reported conventional feed-forward TIA, the proposed automatic-gain-control feed-forward TIA(AFF-TIA) extends the input dynamic range 25 dB wider by employing a 4-level automatic gain control circuit. Measured results demonstrate the linearly varying transimpedance gain of 47 to $72dB{\Omega}$, input dynamic range of 1:100, the bandwidth of $${\geq_-}670MHz$$, the equivalent input referred noise current spectral density of 6.9 pA/${\surd}$HZ, the maximum sensitivity of -26.8 dBm for $10^{-12}BER$, and the power consumption of 27.6 mW from a single 1.8-V supply. The dual-channel chip occupies the area of $1.0{\times}0.73mm^2$ including I/O pads.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.7
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• pp.1086-1093
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• 2001

A new linearization technique for RF high-power amplifiers(HPAs) using n-th order error signal generator (ESGn) is proposed. The n-th order ESG generates an error signal based on the complex envelope transfer characteristics of the HPA, which is combined at the output of the HPA. Therefore, the higher-order nonlinearlities are not affected by the ESG$\_$n/ and the stability of the linearized system is guaranteed due to the inherent open-loop configuration. Moreover, the output delay loss can be avoided, because the error signal is generated with the input signal of the HPA. The IMD(intermodulation distortion) improvement obtained applying the ESG$\_$7/ to 5 W class A HPA in cellular band demonstrates the feasibility of the proposed postdistortion system.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.39-46
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• 2016

This paper describes the third order feedforward delta-sigma modulator with inverter-based integrators and a 1.5bit comparator for the application of audio signal processing. The proposed 3rd-order delta-sigma modulator is multi-bit structure using 1.5 bit comparator instead of operational amplifier. This delta-sigma modulator has high SNR compared with single-bit 4th-order delta-sigma modulator in a low OSR. And it minimizes power consumes and simplified circuit structure using inverter-based integrator and using inverter-based integrator as analogue adder. The modulator was designed with 0.18um CMOS standard process and total chip area is $0.36mm^2$. The measured power cosumption is 28.8uW in a 0.8V analog supply and 66.6uW in a 1.8V digital supply. The measurement result shows that the peak SNDR of 80.7 dB, the ENOB of 13.1bit and the dynamic range of 86.1 dB with an input signal frequency of 2.5kHz, a sampling frequency of 2.56MHz and an oversampling rate of 64. The FOM (Walden) from the measurement result is 269 fJ/step, FOM (Schreier) was calculated as 169.3 dB.