• ETRI Journal
• /
• v.34 no.3
• /
• pp.478-481
• /
• 2012

Testing memory and repairing faults have become increasingly important for improving yield. Redundancy analysis (RA) algorithms have been developed to repair memory faults. However, many RA algorithms have low analysis speeds and occupy memory space within automatic test equipment. A fast RA algorithm using simple calculations is proposed in this letter to minimize both the test and repair time. This analysis uses the grouped addresses in the faulty bitmap. Since the fault groups are independent of each other, the time needed to find solutions can be greatly reduced using these fault groups. Also, the proposed algorithm does not need to store searching trees, thereby minimizing the required memory space. Our experiments show that the proposed RA algorithm is very efficient in terms of speed and memory requirements.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.8 no.5
• /
• pp.265-272
• /
• 2013

This paper addresses a control allocation method for fault-tolerant control by redistributing redundant control surfaces. The proposed method is based on a classical daisy chain approach for the compensation of faulty actuators. The existing daisy chain method calculates a desired moment according to a number of actuator groups. However, this method has a significant limitation; that is, any faulty actuator belonging to the last actuator group cannot be compensated, since there is no more redundant actuator group that can be used to generate the required moments. In this paper, a modified daisy chain method is proposed to overcome this problem. Using the proposed method, the order of actuator groups is readjusted so that actuator groups containing any faulty actuator are always placed in an upper group instead of the last one. A set of simulation results with an F-18 HARV aircraft demonstrate that the proposed method can achieve better performance than the existing daisy chain method.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.44 no.3
• /
• pp.256-265
• /
• 2016

Software based fault tolerance techniques are designed to allow a system to tolerate software faults in the system. Fault tolerance techniques are divided into two groups : software based fault tolerance techniques and hardware based fault tolerance techniques. We need a proper design method according to characteristics of the system. In this paper, the concepts of software based fault tolerance techniques for Dual Flight Control Computer are described. For software based fault tolerance design, we classified software failure, designed a way for failure detection and the way of recovery. Eventually the effectiveness of software based fault tolerance techniques was verified through the Software Test Environment(STE).

• Progress in Superconductivity and Cryogenics
• /
• v.10 no.2
• /
• pp.30-33
• /
• 2008

Several kinds of superconducting fault current limiters (SFCLs), which reduces huge fault current, have been developing by many research groups. The SFCL has no impedance during normal operation, so it dose not give any influence to electric power system. The resistive type SFCL reduces the fault current with the impedance generated in the superconducting part of the SFCL when the fault current exceeds the critical current of SFCL. In this paper, a new type resistive SFCL made of bifilar coil wound with two different high-Tc superconducting (HTS) wires in parallel. Although a bifilar coil has theoretically no inductance, the bifilar coil made in this paper could generate inductance at fault. The specifications of the used two wires were considerably different, thus current distribution between the two HTS wire was different at fault. When the fault current exceeded the critical current of one wire in the bifilar coil, the momentary sharp increase of impedance was detected. Base on the results, a new resistive type SFCL can generate not only resistance but also inductance, which can be used to control a fault current in the future.

• 전기의세계
• /
• v.21 no.4
• /
• pp.39-44
• /
• 1972

This paper describes a new approach for minimizing working memory spaces without loosing too much amount of computing time in the analysis of power system faults. This approach requires the decomposition of alrge power system into several small groups of subsystems, forms individual bus impedance matrics, store them in the auxiliary memory, later assembles them to the original total system by algorithms. And also the approach uses techniques for diagonalizing primitive impedances and expanding the system bus impedance matrices by adding a fault bus. These scheme ensures a remarkable savings of working storage and continous computations of fault currents and voltages with the voried fault locations.

• Proceedings of the Earthquake Engineering Society of Korea Conference
• /
• 2002.03a
• /
• pp.28-35
• /
• 2002

The probabilistic seismic hazard analysis for engineering needs several active fault parameters as input data. Fault slip rates, the segmentation model for each fault, and the date of the most recent large earthquake in seismic hazard analysis are the critical pieces of information required to characterize behavior of the faults. Slip rates provide a basis for calculating earthquake recurrence intervals. Segmentation models define potential rupture lengths and are inputs to earthquake magnitude. The most recent event is used in time-dependent probability calculations. These data were assembled by expert source-characterization groups consisting of geologists, geophysicists, and seismologists evaluating the information available for earth fault. The procedures to prepare inputs for seismic hazard are illustrated with possible segmentation scenarios of capable fault models and the seismic hazards are evaluated to see the implication of considering capable faults models.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
• /
• 2005.11b
• /
• pp.200-203
• /
• 2005

Ball bearings not only sustain the system, but permit the rotational component to rotate. Excessive radial or axial load and many other reasons can cause faults to be created and grown rapidly in each component. The grown faults make noise and vibration, which can make the system unstable. Therefore, it is important to detect faults as early as possible. For this reason, there have been many researches on fault detection method of early faults in a ball bearing. The fault defection methods can be categorized to several groups by signal processing methods. Not all the methods are efficient for finding early faults. We select representative methods known as efficient for detecting early faults and compare the results for inspecting which method is effective.

• Smart Structures and Systems
• /
• v.19 no.4
• /
• pp.415-429
• /
• 2017

This paper focuses on the impact of the wave passage effect on the long-span bridge. In order to make the wave passage effect more obvious, ground motion samples are selected from the near-fault ground motion of the 1999 Chi-Chi earthquake and an arch bridge with a 280m main span is selected as a bridge sample. The motion ground samples are divided into two groups according to the characteristics of near-fault. A sequence of fragility curves is developed. It is shown that the seismic damage is increased by the wave passage effect and the increase is more obvious in the near-fault ground motion.

• The Journal of the Petrological Society of Korea
• /
• v.1 no.1
• /
• pp.25-33
• /
• 1992

The southwestern part of Gyeonggi Massif consists mainly of Archean Seosan and Daesan Groups, and Paleoproterozic Bucheon Group with Bucheon and Seosan gneiss complexes which are members of Gyeonggi gneiss complex. In the eastern part of Dangjin fault, Mesoproterozoic Anyang Group and Anyang granite gneiss occur, and in the western part of the fault Taean Group uncomformably overlies Archean and Paleoproterozoic Groups. Metamorphic facies of Archean Groups is mainly upper amphibolite facies which was overprinted by the second amphibolite facies metamorphism and the third greenschist facies metamorphism. Bucheon and Anyang Groups belong to amphibolite and greenschist facies and are partly overprinted by greenschist facies metamorphism which is characteristic for Taean and Daedong Groups.

• Journal of Electrical Engineering and Technology
• /
• v.13 no.6
• /
• pp.2485-2492
• /
• 2018

The rapid development of large-scale integrated circuits has brought great challenges to the circuit testing and diagnosis, and due to the lack of exact fault models, inaccurate analog components tolerance, and some nonlinear factors, the analog circuit fault diagnosis is still regarded as an extremely difficult problem. To cope with the problem that it's difficult to extract fault features effectively from masses of original data of the nonlinear continuous analog circuit output signal, a novel approach of feature extraction and dimension reduction for analog circuit fault diagnosis based on wavelet packet decomposition, local linear embedding algorithm, and clone selection algorithm (WPD-LLE-CSA) is proposed. The proposed method can identify faulty components in complicated analog circuits with a high accuracy above 99%. Compared with the existing feature extraction methods, the proposed method can significantly reduce the quantity of features with less time spent under the premise of maintaining a high level of diagnosing rate, and also the ratio of dimensionality reduction was discussed. Several groups of experiments are conducted to demonstrate the efficiency of the proposed method.