• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.1100-1112
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• 1998

In this paper, a novel method of minimizing the phase error is proposed. A DP-PLL system using this method is implemented and its performacnce is investigated, too. The DP-PLL system detects the phase error between reference clock and locally generated system clock. The phase difference is then reported as a PEV(Phase Error Variation), which is propoced from the delayted n-tap rising dege clock circuit with 5ns resolution in the phase detector. The algorithm is used to track the optimal DAC coefficients, which are adjusted from sample to sample in such a way as to minimize the PEV. The proposed method is found to have remarkable good potential for fast and accurate phase error tracking characteristic. The algorithm shows good performance to supress the low frequency jitter.-ending points, we design new basis functions based on the Legendre polynomial and then transform the error signals with them. When applied to synthetic images such as circles, ellipses and etc., the proposed method provides, in overall, outstanding results in respect to the transform coding gain compared with DCT and DST. And in the case when applied to natural images, the proposed method gives better image quality over DCT and comparable results with DST.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.11
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• pp.1264-1271
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• 2012

Fast tracking is important for high-speed data transmission in high-speed mobile environment such as high speed rail and vehicular. Digital retrodirective array antenna is possible to do automatically beam tracking because it can control the phase information of the output signal toward opposite direction to input signal without no a priori knowledge of the arrival direction. Also, Digital retrodirective array antennas has merit that it is easy to upgrade and modify compare with analogue retrodirective array antennas. In this paper, we analyze the BER performance of digital retrodirective array antenna under AWGN environment and multipath signal. Simulation results show correct phase estimation and conjugation of retrodirective array antenna by using phase detector block. Also, phase conjugation technique has better BER performance about 1 dB at source than that of without phase conjugation when phase lag is $15^{\circ}$ in AWGN environment. This paper also discusses effect of the presence of multipath signal. Phase and amplitude error about direction of direct signal occurs when retrodirective array system is affected by interference and multipath signal in the presence of multipath signal.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.168-180
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• 2018

In order to achieve the high quality output voltage of single-phase voltage source inverters, in this paper an Adaptive Complementary Sliding Mode Control (ACSMC) is proposed. Firstly, the dynamics model of the single-phase inverter with lumped uncertainty including parameter variations and external disturbances is derived. Then, the conventional Sliding Mode Control (SMC) and Complementary Sliding Mode Control (CSMC) are introduced separately. However, when system parameters vary or external disturbance occurs, the controlling performance such as tracking error, response speed et al. always could not satisfy the requirements based on the SMC and CSMC methods. Consequently, an ACSMC is developed. The ACSMC is composed of a CSMC term, a compensating control term and a filter parameters estimator. The compensating control term is applied to compensate for the system uncertainties, the filter parameters estimator is used for on-line LC parameter estimation by the proposed adaptive law. The adaptive law is derived using the Lyapunov theorem to guarantee the closed-loop stability. In order to decrease the control system cost, an inductor current estimator is developed. Finally, the effectiveness of the proposed controller is validated through Matlab/Simulink and experiments on a prototype single-phase inverter test bed with a TMS320LF28335 DSP. The simulation and experimental results show that compared to the conventional SMC and CSMC, the proposed ACSMC control strategy achieves more excellent performance such as fast transient response, small steady-state error, and low total harmonic distortion no matter under load step change, nonlinear load with inductor parameter variation or external disturbance.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.1218-1220
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• 1992

This paper presents the three section sliding mode control algorithm based on variable structure current controller design in a synchronous frame and indirect field oriented control method, and applies it to the position control of induction motor. This control scheme solves the problem of robustness loss during the reaching phase that occurs in a conventional VSC strategy, and ensures the stable sliding mode and robustness enhancement throughout an entire response. As the performance of a VSI fed induction motor drives depends on the characteristics of inner loop current controller, it is desired that the current controller have the fast tracking and robust nature. Therefore, we introduced the voltage mapping table based on the concept of voltage space vector for variable structure current control, and implemented fully digital control system using 16-bit microcontroller with on-chip peripherals without additional processing circuits. Simulation and experimental results confirm the validity of this control scheme for robust AC servo drive system of VSI fed induction motor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7A
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• pp.1028-1035
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• 1999

To increase the throughput of data transmission in burst-mode TDMA communication systems and also to get a good BER performance at the same time, it is essential to rapidly acquire the carrier while keeping the desirable tracking performance. To achieve this goal, in this paper, a new decision-directed carrier recovery algorithm is presented. The proposed scheme does not incorporate the PLL and suppress the Gaussian random process of input noise by the pre-stage low pass filter so as to get both the fast acquisition and a good performance. Through computer simulations, the performance of the scheme is analyzed with respect to the acquisition time and bit error rate. The cycle slip in the proposed scheme is seldom observed at very low SNR environment in contrast to the previous proposed one. Because of this merit, it is not required to do the differential encoding and decoding in the proposed scheme.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.229-234
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• 2006

Acquisition is to detect the presence of the GPS signal. Once the signal is detected, the estimated frequency and code phase are passed to a tracking loop to demodulate the navigation data. In order to detect the weak signal, multiple length of data integration is always needed. In this paper, we present five different acquisition approaches based on circular correlation and Fast Fourier Transform (FFT), using coherent as well as non-coherent integration techniques for the multiple length of collected GPS satellite signal. Moreover a general approach of determining the acquisition threshold is introduced based on noise distribution which has been proved effective, and independent of the hardware. In the end of this paper, the processing speed and acquisition gain of each method are illustrated, compared, and analyzed. The results show that coherent approach is much more time consuming compared to noncoherent approaches, and in the case of multiple length of data integration from 2ms to 8ms, the processing times consumed by the fastest non-coherent acquisition method are only 25.87% to 1.52% in a single search, and 34.76% to 1.06% in a global search of those in the coherent acquisition. However, coherent acquisition also demonstrates its better performance in the acquisition gain, and in the case of 8ms of data integration it is 4.23 to 4.41 dB higher than that in the non-coherent approaches. Finally, an applicable scheme of combining coherent and non-coherent acquisition approaches in the development of a real-time Software GPS receiver in the University of Tokyo is provided.