• 대한전기학회논문지
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• 제41권8호
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• pp.893-901
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• 1992

In this paper, we propose a new resolver-to digital(R/D) conversion method, in which a bang-bang type phase comparator is employed for fast tracking. We eliminate from the R/D conversion loop the low-pass filter which is needed to reject carrier signal and noise. Instead, we employ two prefilters outside the R/D conversion loop that take the role of the low-pass filter. Thereby, we can construct a fast and accurate tracking R/D converter. Some simulation and experimental results as well as mathematical performance analysis are presented to demonstrate the superior tracking performance of our R/D converter over conventional tracking R/D converters.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권4호
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• pp.506-517
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• 2015

This paper presents a 1.248 Gb/s - 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is $0.01{\mu}s$ the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a $0.11{\mu}m$ CMOS process, and the die area is $600{\mu}m{\times}250{\mu}m$. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are $35.24ps_{p-p}$ and $4.25ps_{rms}$ respectively for HS-G2 mode.

• 전기학회논문지
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• 제60권7호
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• pp.1331-1338
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• 2011

This paper proposes a method for frequency control of islanded microgrid with battery energy storage system. For frequency control of islanded microgrid, battery energy storage system uses a phase locked loop algorithm with positive sequence components for a fast frequency estimation. Microgrid is a power system with small inertia because it has small capacity generators and inverter systems for renewable energy. So, Islanded microgrid's frequency varies fast and large as small generation and load changes. To reduce frequency variation of islanded microgrid, it needs a device with fast frequency response. For fast frequency response, a fast frequency tracking is important. To show the validation of proposed fast frequency tracking algorithm, battery energy storage system with proposed algorithm is tested in microgrid pilot plant.

• International Journal of Control, Automation, and Systems
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• 제5권2호
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• pp.161-169
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• 2007

The PLL equivalent augmented system incorporated with state feedback is proposed in this paper. The optimal value of filter time constant of loop filter in the phase-locked loop control system and the optimal state feedback gain designed by using linear quadratic regulator approach are derived. This approach allows the PLL control system to employ the large value of the phase-frequency gain $K_d$ and voltage control oscillator gain $K_o$. In designing, the structure of phase-locked loop control system will be rearranged to be a phase-locked loop equivalent augmented system by including the structure of loop filter into the process and by considering the voltage control oscillator as an additional integrator. The designed controller consisting of state feedback gain matrix K and integral gain $k_1$ is an optimal controller. The integral gain $k_1$ related to weighting matrices q and R will be an optimal value for assigning the filter time constant of loop filter. The experimental results in controlling the second-order lag pressure process using two types of loop filters show that the system response is fast without steady-state error, the output disturbance effect rejection is fast and the tracking to step changes is good.

• Journal of Electrical Engineering and Technology
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• 제5권4호
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• pp.606-613
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• 2010

This paper proposes a novel current-based maximum power point tracking (CMPPT) method for a single-phase photovoltaic power conditioning system (PV PCS) by using a modified incremental conductance method. The CMPPT method simplifies the entire control structure of the power conditioning system and uses an inherent current source characteristic of solar cell arrays. Therefore, it exhibits robust and fast response under a rapidly changing environmental condition. Digital phase locked loop technique using an all-pass filter is also introduced to detect the phase of grid voltage, as well as the peak voltage. Controllers of dc/dc boost converter, dc-link voltage, and dc/ac inverter are designed for coordinated operation. Furthermore, a current control using a pseudo synchronous d-q transformation is employed for grid current control with unity power factor. A 3 kW prototype PV PCS is built, and its experimental results are given to verify the effectiveness of the proposed control schemes.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.520-523
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• 2004

A phase-locked loop control system designed by using the linear quadratic regulator approach is presented in this paper. The system thus designed is optimal system when system is in locked state and the parameter value of loop filter which is an active PI filter can be obtained easily. By considering the structure of loop filter of phase-locked loop is included in the process to be controlled, a type 1 servo system can be constructed when voltage control oscillator is considered as an integrator. The integral gain of the proposed system obtained by linear quadratic regulator approach can be used as an optimal value to design the parameter of loop filter. The implemented result in controlling the second-order lag pressure process by using the proposed scheme show that the system response is fast with no overshoot and no steady-state error. Furthermore, the experimental results are also shown in term of output disturbance effect rejection, tracking and process parameter changed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.387-394
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• 2016

This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in a 65 nm CMOS process, the proposed DLL occupies $0.0432mm^2$, and consumes 3.7 mW from a 1.2-V supply at 2 GHz.

• Journal of Power Electronics
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• 제14권2호
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• pp.392-401
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• 2014

A fast-transient repetitive control strategy for a three-phase shunt active power filter is presented in this study to improve dynamic performance without sacrificing steady-state accuracy. The proposed approach requires one-sixth of the fundamental period required by conventional repetitive control methods as the repetitive control time delay in the synchronous reference frames. Therefore, the proposed method allows the system to achieve a fast dynamic response, and the program occupies minimal storage space. A proportional-integral regulator is also added to the current control loop to eliminate arbitrary-order harmonics and ensure system stability under severe harmonic distortion conditions. The design process of the corrector in the fast-transient repetitive controller is also presented in detail. The LCL filter resonance problem is avoided by the appropriately designed corrector, which increases the margin of system stability and maintains the original compensation current tracking accuracy. Finally, experimental results are presented to verify the feasibility of the proposed strategy.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2018년도 전력전자학술대회
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• pp.382-383
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• 2018

To increase the efficiency of a wind energy conversion system (WECS), the maximum power point tracking (MPPT) algorithm is usually employed. This paper proposes an optimal MPPT algorithm which tracks a sudden wind speed change condition fast. The proposed method can be implemented without the prior information on the wind turbine parameters, generator parameters, air density or wind speed. By investigating the directions of changes of the mechanical output power in wind turbine and rotor speed of the generator, the proposed MPPT algorithm is able to determine an optimal speed to achieve the maximum power point. Then, this optimal speed is set to the reference of the speed control loop. As a result, the proposed MPPT algorithm forces the system to operate at the maximum power point by using a three-phase converter. The simulation results based on the PSIM are given to prove the effectiveness of the proposed method.

• 대한전자공학회논문지SD
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• 제45권12호
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• pp.65-72
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• 2008

이 논문은 seamless 주파수 트래킹 방법을 이용한 새로운 이중 루프 디지털 PLL(DPLL)을 제안한다. Coarse 루프와 fine 루프로 구성되는 이중 루프 구조는 빠른 획득 시간과 스위칭 잡음 억제를 위하여 successive approximation register기법과 TDC 회로를 사용하였다. 제안된 DPLL은 입력 주파수의 long-term 지터에 따른 지터 특성을 보상하기 위하여 Coarse와 fine의 코드 변환 주파수 트래킹 방법을 새로이 추가하였다. 또한, 제안된 DPLL은 넓은 주파수 동작 범위와 낮은 지터 특성 위하여 전류 제어 발진기와 V-I 변환기로 구성되는 전압제어 발진기를 채택하였다. 제안된 DPLL은 동부 하이텍 $0.18-{\mu}m$ CMOS 공정으로 구현하였으며 1.8V의 공급전압에서 0.4-2GHz의 넓은 동작 주파수 범위와 $0.18mm^2$의 적은 면적을 가진다. H-SPICE 시뮬레이션을 통하여, DPLL은 2GHz의 동작 주파수에서 18mW 파워소비와 전원잡음이 없는 경우 3psec이하의 p-p period 지터를 확인하였다.