• The KIPS Transactions:PartC
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• v.16C no.1
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• pp.13-20
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• 2009

Recently, as traffic flooding attacks such as DoS/DDoS and Internet Worm have posed devastating threats to network services, rapid detection and proper response mechanisms are the major concern for secure and reliable network services. However, most of the current Intrusion Detection Systems (IDSs) focus on detail analysis of packet data, which results in late detection and a high system burden to cope with high-speed network traffic. In this paper we propose an SNMP-based lightweight and fast detection algorithm for traffic flooding attacks, which minimizes the processing and network overhead of the detection system, minimizes the detection time, and provides high detection rate. The attack detection algorithm consists of three consecutive stages. The first stage determines the detection timing using the update interval of SNMP MIB. The second stage analyzes attack symptoms based on correlations of MIB data. The third stage determines whether an attack occurs or not and figure out the attack type in case of attack.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.292-301
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• 2001

IDDQ Testing is a very effective testing method to detect many kinds of physical defects occurred in CMOS VLSI circuits. In this paper, we consider the most commonly occurring bridging faults in current CMOS technologies and develop pattern generator for IDDQ testing using efficient IDDQ test algorithms. The complete set of bridging faults between every pair of all nodes(internal and external nodes) within circuit under test is assumed as target fault model. The merit of considering the complete bridging fault set is that layout information is not necessary. Implemented test pattern generator uses a new neighbor searching algorithm and fault collapsing schemes to achieve fast run time, high fault coverage, and compact test sets. Experimental results for ISCAS benchmark circuits demonstrate higher efficiency than those of previous methods.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.3
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• pp.103-110
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• 2008

In this paper, an efficient butterfly structure for 8K/2K-Point Radix-4 FFT algorithm using CORDIC(coordinate rotation digital computer) is proposed. It is shown that CORDIC can be efficiently used in twiddle factor calculation of the Radix-4 FFT algorithm. The Verilog-HDL coding results for the proposed CORDIC butterfly structure show 36.9% cell area reduction comparison with those of the conventional multiplier butterfly structure. Furthermore, the 8K/2K-point Radix-4 pipeline structure using the proposed butterfly and delay commutators is compared with other conventional structures. Implementation coding results show 11.6% cell area reduction. Due to its efficient processing scheme, the proposed FFT structure can be widely used in large size of FFT like OFDM Modem.

• Journal of IKEEE
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• v.20 no.1
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• pp.89-93
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• 2016

In this paper, we proposed SIMT based Image Signal Processor which can apply various image preprocessing algorithms and allow parallel processing of application programs such as image recognition. Conventional ISP has the hard-wired image enhancement algorithm of which the processing speed is fast, but there was difficult to optimize performance depending on various image processing algorithms. The proposed ISP improved the processing time applying SIMT architecture and processed a variety of image processing algorithms as an instruction based processor. We used Xilinx Virtex-7 board and the processing time compared to cell multicore processor, ARM Cortex-A9, ARM Cortex-A15 was reduced by about 71 percent, 63 percent and 33 percent, respectively.

• Journal of IKEEE
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• v.21 no.4
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• pp.358-367
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• 2017

Advanced Driver Assistance Systems(ADAS), such as Front Collision Warning System (FCWS) are currently being developed. FCWS require high processing speed because it must operate in real time while driving. In addition, a low-power system is required to operate in an automobile embedded system. In this paper, FCWS is implemented in CPU-FPGA architecture in embedded system to enable real-time processing. The lane detection enabled the use of the Inverse Transform Perspective (IPM) and sliding window methods to operate at fast speed. To detect the vehicle, a Convolutional Neural Network (CNN) with high recognition rate and accelerated by parallel processing in FPGA is used. The proposed architecture was verified using Intel FPGA Cyclone V SoC(System on Chip) with ARM-Core A9 which operates in low power and on-board FPGA. The performance of FCWS in HD resolution is 44FPS, which is real time, and energy efficiency is about 3.33 times higher than that of high performance PC enviroment.

• Journal of the Korea Society of Computer and Information
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• v.16 no.3
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• pp.9-15
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• 2011

U-healthcare system has an aim to provide reliable and fast medical services for patient regardless of time and space by transmitting to doctors a large quantity of vital signs collected from sensor networks. Existing u-healthcare systems can merely monitoring patients' health status. In this paper, we describe the implementation and validation of a prototype of a u-health monitoring system based on a wireless sensor network. This system is easy to derive physiologically meaningful results by analyzing rapidly vital signs. The monitoring system sends only the abnormal data of examinee to the service provider. This technique can reduces the wireless data packet overload between a monitoring part and service provider. The real-time bio-signal monitoring system makes possible to implement u-health services and improving efficiency of medical services.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.5
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• pp.103-115
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• 2014

Mobile-Office is the IT office that enables people handle their business anywhere and anytime without going to head office. It has propagated rapidly in domestic and foreign companies as the users who use mobile terminal such as smartphone have increased sharply. Mobile-Office is emerging as a new way of conducting business. It requires business environment to be changed to improve business efficiency, as fast-growing mobile-based economies emerges. Small and medium-sized companies's utilization ability for advanced IT technology is insufficient, and limitations exist on capacity of building and investment. They need different development methodologies and utilization methods. The purpose of this study is not only to consider the previous business environment problem on accessibility, mobility, effectiveness, complexity and consolidation, but to search more efficient methods for introducing applications to utilize various smart devices and websites with minimum investment in R&D.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.3C
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• pp.278-286
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• 2010

Motion Compensated Frame Interpolation(MCFI) has been used to reduce motion jerkiness for dynamic scenes and motion blurriness for LCD-panel display as post processing for large screen and full HD(high definition) display. Conventionally, block matching algorithms (BMA) are widely used to do motion estimation for simplicity of implementation. However, there are still several drawbacks. So in this paper, we propose a novel shape-based ME algorithm to increase accuracy and reduce ME computational cost. To increase ME accuracy, we do motion estimation based on shape of moving objects. And only moving areas are included for motion estimation to reduce computational cost. The results show that the computational cost is 25 % lower than full search BMA, while the performance is similar or is better, especially in the fast moving region.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.5B
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• pp.469-479
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• 2009

The GEM frame is used a mean to deliver the variable length user data and consists of the header and the payload in the G-PON system. The HEC field of header protects contents of the header and is used to maintain GEM frame synchronization at the same time. When an LCDG (Loss of GEM Channel Delineation) occurs while receiving frames, the receiver have to discard corrupted frames until acquiring the synchronization again. Accordingly, high-speed synchronization method is required to minimize the frame loss. In this paper, we suggest not only a main state machine but a sub-state machine to reduce the frame loss when undetectable errors occurred in the GEM header. Also, we provide a more efficient and fast parallel structure to detect the starting point of the header. Finally, the proposed method is implemented with the FPGA and verified by the logic analyzer.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.4
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• pp.430-441
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• 2002

Video object segmentation is an important component for object-based video coding scheme such as MPEG-4. In this paper, a robust algorithm for segmentation of moving objects in video sequences and VOP(Video Object Planes) extraction is presented. The points of this paper are detection, of an accurate object boundary by associating moving object edge with spatial object edge and generation of VOP. The algorithm begins with the difference between two successive frames. And after extracting difference image, the accurate moving object edge is produced by using the Canny algorithm and morphological operation. To enhance extracting performance, we app]y the morphological operation to extract more accurate VOP. To be specific, we apply morphological erosion operation to detect only accurate object edges. And moving object edges between two images are generated by adjusting the size of the edges. This paper presents a robust algorithm implementation for fast moving object detection by extracting accurate object boundaries in video sequences.