• Proceedings of the Korean Society of Computer Information Conference
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• 2010.07a
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• pp.35-38
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• 2010

본 논문에서는 일상생활 속에서 무자각적으로 생체신호를 측정하고 분석하여 감성을 평가할 수 있는 임베디드 시스템에 관하여 연구하였다. 지속적으로 변화하는 감성을 일관적이며 신뢰성이 높은 생리적인 방법으로 평가하기 위해 심전도(ECG:Electrocardiogram), 맥파(PPG:Photoplethysmogram)의 두 가지 생체신호를 측정하고, 무선전송(Bluetooth) 장치를 이용하여 측정한 생체신호를 실시간으로 노트북PC로 전송하여 분석하였다. 생체신호의 분석방법은 FFT(Fast Fourier Transform)과 전력스펙트럼밀도(Power Spectrum Density)를 이용한 주파수 분석방법으로 두 생체신호의 특정 주파수 대역이 가지는 자율신경계의 활성도의 비율을 분석하여 비교 연구하였다. 또한 보다 빠르고 정확한 감성을 평가하기 위하여 분석알고리즘의 연산을 최소화 하였으며 그래프를 이용한 분석결과의 시각화를 하였다. 본 논문에서는 무자각적인 생체신호 측정 시스템을 이용하여 다양한 상황에서 생체신호를 측정하고, 개발한 분석 알고리즘으로 분석한 결과의 차이를 연구하여 정확도 및 신뢰도를 기준으로 감성을 평가하기 위한 분석 시스템을 평가하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.05a
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• pp.421-422
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• 2021

In this paper, we develop an ultra-sensitive sensor and signal analysis system to measure the load on the wrist. The ultra-sensitive sensor inspired by the organs of a spider is manufactured and the measured signal attached to the wrist is analyzed using FFT (Fast Fourier Transform) and a fuzzy system.

• Journal of Power Electronics
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• v.13 no.1
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• pp.170-176
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• 2013

Power converters produce a vast range of harmonics, subharmonics and interharmonics. Harmonics analyzing tools based on the Fast Fourier Transform (FFT) assume that only harmonics are present and the periodicity intervals are fixed, while these periodicity intervals are variable and long in the presence of interharmonics. Using FFT may lead to invalid and undesired results due to the above mentioned issues. They can also lead to problems such as frequency blending, spectral leakage and the picket-fence effect. In this paper, the group-harmonic weighting (GHW) approach has been presented to identify the interharmonics in a power system. Afterwards, a modified GHW has been introduced to calculate the proper bandwidth for analyzing the various values of interharmonics. Modifying this method leads to more precise results in the FFT of a waveform containing inter harmonics especially in power systems with a fundamental frequency drift or frequency interference. Numerical simulations have been performed to prove the efficiency of the presented algorithm in interharmonics detection and to increase the accuracy of the FFT and the GWH methods.

• Journal of the Korea Institute of Military Science and Technology
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• v.9 no.3
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• pp.116-122
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• 2006

A fast scan digital-IF FFT receiver at the radio communication band is presented for spectrum monitoring applications. It is composed of three parts: RF front-end, fast LO board, and signal processing board. It has about 19GHz/s scan rate, multi frequency resolution from 10kHz to 2.5kHz, and high sensitivity of below -99dBm. The design and performance analysis of the digital-IF FFT receiver are presented.

• Journal of the Korean Institute of Intelligent Systems
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• v.12 no.2
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• pp.135-143
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• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast courier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like {0, 1, 2, 3}. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used toed as LUT(Lood Up Table).

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.298-306
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• 2018

This paper presents a harmonic analysis of the modular multilevel converter (MMC) using a double Fourier series (DFS) algorithm. First, the application of DFS for harmonic calculation in the MMC is made by considering the effect of arm inductor. The analytical results are then confirmed by comparing with the simulation results of using the fast Fourier transform (FFT) algorithm. Finally, distribution of harmonics and total harmonic distortion (THD) in the MMC will be analyzed in three cases: harmonics versus number of levels of MMC, harmonics versus total switching frequency and harmonics versus modulation index. The simulation results are performed in the PSCAD/EMTDC simulation program in order to verify the analytical results obtained by Matlab programming.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.29-35
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• 2017

This paper presents a high-throughput area-efficient mixed-radix fast Fourier transform (FFT) processor using the efficient scheduling schemes. The proposed FFT processor can support 64, 128, 256, and 512-point FFTs for orthogonal frequency division multiplexing (OFDM) systems, and can achieve a high throughput using mixed-radix algorithm and eight-parallel multipath delay commutator (MDC) architecture. This paper proposes new scheduling schemes to reduce the size of read-only memories (ROMs) and complex constant multipliers without increasing delay elements and computation cycles; thus, reducing the hardware complexity further. The proposed mixed-radix MDC FFT processor is designed and implemented using the Samsung 65nm complementary metal-oxide semiconductor (CMOS) technology. The experimental result shows that the area of the proposed FFT processor is 0.36 mm2. Furthermore, the proposed processor can achieve high throughput rates of up to 2.64 GSample/s at 330 MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.11-20
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• 2016

In this paper, we propose the channel estimation scheme for Long Term Evolution-Advanced (LTE-A) downlink system. The proposed scheme uses the fast fourier transform (FFT) interpolation scheme for the user moving at a high speed. The FFT interpolation scheme converts the channel frequency response obtained from least square (LS) or minimum mean square error (MMSE) channel estimation scheme to time domain channel impulse response by taking the inverse FFT (IFFT). After windowing the channel response in the time domain, we can obtain the channel frequency response by taking the FFT. We perform the system level simulation based on 20MHz bandwidth of 3GPP LTE-A downlink system. Simulation results show that the proposed channel estimation scheme can improve signal-to-noise-plus-interference ratio (SINR), throughput, and spectral efficiency of conventional system.

• Journal of Sensor Science and Technology
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• v.32 no.4
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• pp.246-251
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• 2023

Internet of Things (IoT) systems process signals from various sensors using signal processing algorithms suitable for the signal characteristics. To analyze complex signals, these systems usually use signal processing algorithms in the frequency domain, such as fast Fourier transform (FFT), filtering, and short-time Fourier transform (STFT). In this study, we propose a multi-mode sensor signal processor (SSP) accelerator with an FFT-based hardware design. The FFT processor in the proposed SSP is designed with a radix-2 single-path delay feedback (R2SDF) pipeline architecture for high-speed operation. Moreover, based on this FFT processor, the proposed SSP can perform filtering and STFT operation. The proposed SSP is implemented on a field-programmable gate array (FPGA). By sharing the FFT processor for each algorithm, the required hardware resources are significantly reduced. The proposed SSP is implemented and verified on Xilinxh's Zynq Ultrascale+ MPSoC ZCU104 with 53,591 look-up tables (LUTs), 71,451 flip-flops (FFs), and 44 digital signal processors (DSPs). The FFT, filtering, and STFT algorithm implementations on the proposed SSP achieve 185x average acceleration.

• Journal of Korea Multimedia Society
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• v.24 no.11
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• pp.1552-1559
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• 2021

Convolution neural networks (CNNs) show notable performance in image processing and are used as representative core models. CNNs extract and learn features from large amounts of train dataset. In general, it has a structure in which a convolution layer and a fully connected layer are stacked. The core of CNN is the convolution layer. The size of the kernel used for feature extraction and the number that affect the depth of the feature map determine the amount of weight parameters of the CNN that can be learned. These parameters are the main causes of increasing the computational complexity and memory usage of the entire neural network. The most computationally expensive components in CNNs are fully connected and spatial convolution computations. In this paper, we propose a Fourier Convolution Neural Network that performs the operation of the convolution layer in the Fourier domain. We work on modifying and improving the amount of computation by applying the fast fourier transform method. Using the MNIST dataset, the performance was similar to that of the general CNN in terms of accuracy. In terms of operation speed, 7.2% faster operation speed was achieved. An average of 19% faster speed was achieved in experiments using 1024x1024 images and various sizes of kernels.