• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.47-48
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• 2006

In this paper, intrinsic n channel MOSFETs with external parasitic components are modeled. Using sensitivity analysis, effective parasitic components are tested and the optimized model is extracted. The extracted model is fitted to the measured S-parameters with different channel width. Based on this methodology, this method, external parasitic components that affect MOSFET operations can be analyzed and modeled.

• Journal of IKEEE
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• v.21 no.3
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• pp.260-263
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• 2017

Based on several CPU cores, an SoC including ADCs, DC-DC converter and 2M-byte SRAM is proposed in this paper. The CPU core consists of a 12-bit MENSA, a 32-bit Symmetric multi-core processor, as well as 16-bit CDSP. To eliminate the external SDRAM memory, internal 2M-byte SRAM is implemented. Because the SRAM normally occupies huge area, the parasitic components reduce the speed of SoC. In this work, the SRAM blocks are divided into small pieces to reduce the parasitic components. The proposed SoC is developed in a standard 55nm CMOS process and the speed of SoC is 200MHz.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.85-88
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• 2001

This paper suggests an improved switch architecture for the rechargeable battery protection IC. In the existing protection IC, charging and discharging switches composed of the CMOS transistor and the diode are external components. It is difficult to integrate the switches in a CMOS process due to the large chip-size overhead and inevitable parasitic effects. In this paper, we propose a new switch architecture of the MOSFET's 'diode connection' method. The performance and chip-size overhead are proved to be adequate for the fully integrated protection IC.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.490-492
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• 2010

A swing level controlled voltage-mode transmitter is proposed to support a stub series-terminated logic channel with center-tapped termination. This transmitter provides a swing level control to support the diagnostic mode and improve the signal integrity in the absence of the destination termination. By using the variable parallel termination, the proposed transmitter maintains the constant output impedance of the source termination while the swing level is controlled. Also, the series termination using an external resistor is used to reduce the impedance mismatch effect due to the parasitic components of the capacitor and inductor. To verify the proposed transmitter, the voltage-mode driver, which provides eight swing levels with the constant output impedance of about $50{\Omega}$, was implemented using a 70nm 1-poly 3-metal DRAM process with a 1.5V supply. The jitter reduction of 54% was measured with the swing level controlled voltage-mode driver in the absence of the destination termination at 1.6-Gb/s.