• Proceedings of the Korea Information Processing Society Conference
• /
• 2004.05a
• /
• pp.377-380
• /
• 2004

본 논문에서 우리는 지능형 e-비즈니스를 효과적으로 수행하기 위한 시맨틱 웹 서비스 아키텍처의 구성요소인 마크업인 OWL-S를 CLP(Constraint Logic Program) RuleML로의 확장 및 통합방안에 관한 연구결과를 제시한다. 우리의 주 공헌은 OLP(Ordinary Logic Program), SCLP(Situated Courteous Logic Program) 및 CLP(Constraint Logic Program) 사이의 표현력과 계산력을 비교 및 분석한 근거를 바탕으로 하여 시맨틱 웹, 웹 서비스 그리고 규칙표현 모두가 함께 사용될 수 있는 근거를 제공하였다는 것이다. 본 논문에서 제안된 접근법은 온톨로지를 마크업하기 위한 노력과 규칙을 표현하기 위한 노력이 자연스러운 방법으로 통합될 수 있는 근간을 마련할 뿐만 아니라 규칙들을 이용하여 온톨로지들을 보완하고, 규칙들에서 사용되는 용어들을 온톨로지들에서 정의된 용어들 및 속성들로 표현할 수 있다는 장점을 가진다.

• Korean Journal of Logic
• /
• v.9 no.2
• /
• pp.1-30
• /
• 2006

This paper investigates algebraic semantics for some weak Boolean (wB) logics, which may be regarded as left-continuous t-norm based logics (or monoidal t-norm based logics (MTLs)). We investigate as infinite-valued logics each of wB-LC and wB-sKD, and each corresponding first order extension $wB-LC\forall$ and $wB-sKD\forall$. We give algebraic completeness for each of them.

• Journal of Institute of Control, Robotics and Systems
• /
• v.13 no.4
• /
• pp.352-357
• /
• 2007

This paper deals with modeling method and application of Fuzzy Discrete Event System(FDES). FDES have characteristics which Crisp Discrete Event System(CDES) can't deals with and is constituted with the events that is determined by vague and uncertain judgement like biomedical or traffic control. We proposed Real-time Fuzzy Temporal Logic Framework(RFTLF) to model Fuzzy Discrete Event System. It combines Temporal Logic Framework with Fuzzy Theory. We represented the model of traffic signal systems for intersection to have the property of Fuzzy Discrete Event System with Real-time Fuzzy Temporal Logic Framework and designed a traffic signal controller for smooth traffic flow. Moreover, we proposed the method to find the minimum-time route to reach the desired destination with information obtained in each intersection. In order to evaluate the performance of Real-time Fuzzy Temporal Logic Framework model proposed in this paper, we simulated unit-time extension traffic signal controller model of the latest signal control method on the same condition.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2018.05a
• /
• pp.470-471
• /
• 2018

This paper presents a design method for combinational digital logic systems using time domain based multiplexing and common multi-terminal extension decision diagrams. The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams(DDs), that is the common binary decision diagrams and CMTEDDs. Also, we propose an algorithms to derive common multiple-terminal binary decision diagrams from CBDDs, and CMTEDDs from CMTBDDs. The CMTEDDs over CBDDs is more compactness in terms of number of non-terminal nodes, where the nodes for output selection variables are not included in the non-terminal nodes. In the logic design, each non-terminal nodes of an CBDDs and an CMTEDDs is realized by a multiplexer(MUX). In addition, we compare the proposed TDBM realization with the conventional one.

• The KIPS Transactions:PartA
• /
• v.13A no.1 s.98
• /
• pp.53-56
• /
• 2006

Genetic algorithms(GA), which are based on the idea of natural selection and natural genetics, have proven successful in solving difficult problems that are not easily solved through conventional methods. The classical GA has the problem to spend much time when population is large. Parallel genetic algorithm(PGA) is an extension of the classical GA. The important aspect in PGA is migration and GA operation. This paper presents PGAs that use fuzzy logic. Experimental results show that the proposed methods exhibit good performance compared to the classical method.

• Proceedings of the Korea Contents Association Conference
• /
• 2012.05a
• /
• pp.287-288
• /
• 2012

프로그램의 정적 검증을 위한 명세는 1차 술어 논리(First Order Logic)가 주로 사용된다. 하지만 1차 술어 논리가 모든 정보를 표현할 수가 없기에 이를 보완하기위해 양상논리(Modal Logic)를 사용할 수가 있다. 정적 프로그램 검증을 위해 양상 논리를 이용하여 확장된 BML(Bytecode Modeling Language)은 BIRS로 변환 되어야 한다. 본 논문에서는 확장된 BML을 중간 표현 언어인 BIRS(Bytecode Intermediate Representation Specification)로 표현하기 위하여 BIRS 문법을 확장한다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2012.04a
• /
• pp.265-268
• /
• 2012

검증에 사용하는 명세는 대부분 1차 술어 논리(First Order Logic)로 이루어져 있다. 1차 술어 논리가 자연언어 대부분을 표현하지만 표현하지 못하는 부분도 존재한다. 이를 해결하기위해 양상논리(Modal Logic)를 추가한 명세방법이 존재하지만 간접적인 방법으로만 존재할 뿐 이다. 본 논문에서는, 양상논리를 이용한 명세의 직접적인 표현을 위해 BML(Bytecode Modeling Language)을 확장한다. 이를 통해, 명세정보 표현의 정확성을 향상시킨다.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.32A no.4
• /
• pp.75-84
• /
• 1995

Fault simulators are used for accurate evaluation of fault coverages of digital circuits. But fault simulation becomes time and memory consuming job because computation time is proportional to wquare of size of circuits. Recently, several approximate algorithms for testability analysis have been published to cope with the problems. COP is very fast but cannot be used for sequential circuits, while STAFAN can ve used for sequential circuits but requires large amount of computation because it utilizes logic simulation results. In this paper EXTASEC(An Extension of Testability Analysis for Sequential Circuits) is proposed. It is an extension of COP in the sense that it is the same as COP for combinational circuits, but it can handle sequential circuits, Xicontrollability and backward line analysis are key concept for EXTASEC. Performance of EXTASEC is proven by comparing EXTASEC with a falut simulator, STAFAN, and COP for ISCAS circuits, and the result is demonstated.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
• /
• 2003.05a
• /
• pp.112-115
• /
• 2003

Sub-90nm급 high speed 소자를 위해서는 extension영역의 shallow junction과 sheet 저항의 감소가 필수적이다. 일반적으로 기생저항은 channel저항의 약 10-20%정도를 차지하도록 제작되므로, 이를 최소화하여 optimize하기 위해서는 기생저항에 대한 성분 분리와 이들이 가지는 저항값에 대한 정량적 계산이 이루어져야 한다. 이에 본 논문은 calibration된 TCAD simulation을 통해 90nm급 Tr. 에서 각 영역의 저항성분을 계산, 평가하는 방법을 제시한다. 이 결과, 특히, extension영역의 표면-accumulation부분이 가장 개선이 있어야 할 부분으로 분석되었으며, 이 저항은 gate하부에 존재하는 extension으로부터 발if되는 측면 doping의 tail영역으로 인해 형성되는 것으로,doping의 abruptness가 가장 중요한 factor인 것으로 판단된다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.10a
• /
• pp.687-688
• /
• 2011

This paper presents a design method for combinational digital logic systems using time domain based multiplexing(TDBM) and common multi-terminal extension decision diagrams(CMTEDD). The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams(DDs), that is the common binary decision diagrams(CBDDs) and CMTEDDs. Also, we propose an algorithms to derive common multiple-terminal binary decision diagrams(CMTBDD) from CBDDs, and CMTEDDs from CMTBDDs. The CMTEDDs over CBDDs is more compactness in terms of number of non-terminal nodes, where the nodes for output selection variables are not included in the non-terminal nodes. In the logic design, each non-terminal nodes of an CBDDs and an CMTEDDs is realized by a multiplexer(MUX). In addition, we compare the proposed TDBM realization with the conventional one.