• The KIPS Transactions:PartD
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• v.13D no.1 s.104
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• pp.117-124
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• 2006

Hardware and software codesign framework called PeaCE(Ptolemy extension as a Codesign Environment) was developed. It allows to express both data flow and control flow which is described as fFSM which extends traditional finite state machine. While the fFSM model provides lots of syntactic constructs for describing control flow, it has a lack of their formality and then difficulties in verifying the specification. In order to define the formal semantics of the fFSM, in this paper, firstly the hierarchical structure in the model is flattened and then the step semantics is defined. As a result, some important bugs such as race condition, ambiguous transition, and circulartransition can be formally detected in the model.

• Journal of Institute of Control, Robotics and Systems
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• v.11 no.2
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• pp.152-159
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• 2005

This paper describes the application of a model-based system design method critical to complex intelligent systems, PSARE, to a welding robot development to define its top level architecture. The PSARE model consists of requirement model which describes the core processes(function) of the system, enhanced requirement model which adds technology specific processes to requirement model and allocates them to architecture model, and architecture model which describes the structure and interfaces and flows of the modules of the system. This paper focuses on the detailed procedure and method rather than the detailed domain model of the welding robot. In this study, only the top level architecture of a welding robot was defined using the PSARE method. However, the method can be repeatedly applied to the lower level architecture of the robot until the process which the robot should perform can be clearly defined. The enhanced data flow diagram in this model separates technology independent processes and technology specific processes. This approach will provide a useful base not only for improvement of a class of welding robots but also for development of increasingly complex intelligent real-time systems.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.179-184
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• 1999

A Timing Diagram is almost used to represent the various signals such as an address bus, a data bus, and the control signals during design and analysis of a digital system. But if so, its representation is somewhat complicated and also it is difficult to analyze the operation of the system. In this paper, we proposed the representation method of timing diagrams with the EMFG(Extended Mark Flow Graph). In the EMFG representation of the system operation, the logical states due to the various signals of the system is graphically represented. Therefore the proposal method allows that it is easy to design as well as analyze the system. As examples applied, we represented the memory read cycle of $\mu$PD70320 CPU and the read cycle of MCM60256A memory with the EMFG.