• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.11 s.353
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• pp.210-215
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• 2006

In this paper, we develop the PLL system of the local oscillator system using Gunn oscillator VCO for millimeter wave band receiving system. The local oscillator system consists of the $86{\sim}115GHz$ Gunn. diode oscillator part, the RF processing part including the diplexer and the harmonic mixer, and the DPLL system including Gunn modulator and controller. Based on this configuration, we verify the frequency and power stability of the developed local oscillator system. We developed system which applied to DPLL technique instead of the existing analog PLL method to accomplish this purpose. The developed system for this purpose is tested the frequency and power stability for a long time to confirm performance. Since we confirmed this system that had frequency characteristic of within ${\pm}10Hz$, very fine output drift power characteristic of $0.2{\sim}0.3dBm$ and about 200MHz locking range, it verified suitable for cosmic radio receiving system through the test result.

• Journal of KIISE:Databases
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• v.37 no.6
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• pp.308-314
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• 2010

As the price of flash memory continues to drop and the technology of flash SSD controller innovates, high performance flash SSDs with affordable prices flourish in the storage market. Nevertheless, it is hard to expect that flash SSDs will replace harddisks completely as database storage. Instead, the approach to use flash SSD as a cache for harddisks would be more practical, and, in fact, several hybrid storage architectures for flash memory and harddisk have been suggested in the literature. In this paper, we propose a new approach to use flash SSD as an extended buffer for main buffer in database systems, which stores the pages replaced out from main buffer and returns the pages which are re-referenced in the upper buffer layer, improving the system performance drastically. In contrast to the existing approaches to use flash SSD as a cache in the lower storage layer, our approach, which uses flash SSD as an extended buffer in the upper host, can provide fast random read speed for the warm pages which are being replaced out from the limited main buffer. In fact, for all the pages which are missing from the main buffer in a real TPC-C trace, the hit ratio in the extended buffer could be more than 60%, and this supports our conjecture that our simple extended buffer approach could be very effective as a cache. In terms of performance/price, our extended buffer architecture outperforms two other alternative approaches with the same cost, 1) large main buffer and 2) more harddisks.

• Journal of KIISE:Software and Applications
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• v.37 no.4
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• pp.323-339
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• 2010

The complexity of embedded systems and the effort to develop them has been rising in proportion with their importance. Also, the heterogeneity of the hardware and software parts in embedded systems makes it more challenging to develop. Errors caused by hardware/software interfaces, especially, account for up to 13 percent of failures with an increasing trend. Therefore, verifying the interface between hardware and software in embedded system is one of the most important research areas. However, current approaches such as co-simulation method and model checking have explicit limitations. In this paper, we propose the synthesizable interface co-verification framework for hardware/software co-design. Firstly, we introduce the separate interface specifications for the heterogeneous components to describe hardware design and software design. Our specifications are expressive enough to describe both. We also provide the transformation rules from the software specification to the hardware specification so that the whole system can be described from the software view. Secondly, we address the solution of verifying the interface of the software and hardware design by adopting and extending existing verification-techniques and extending them. In hardware interface verification, we exploit the model checking technique and provide more efficient verification by closing the hardware design from the assumption of the software behavior which is ensured by software verification step. Lastly, we generate the interface codes such as device APIs, device driver, and device controller from the specification so that verified hardware and software codes can be synthesized without extra efforts.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Journal of the Korean Institute of Intelligent Systems
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• v.8 no.5
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• pp.83-97
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• 1998

This paper developes an integrated environment CAD system that can design and implement an accurate and cost-effective FLC automatically. For doing this, an integrated development environment (IDE) (called FADIS; FLC Automatic Design and Implementation Station) is built by the seemless coupling of many existing. CAD tools in an attempt to the FADIS performs various functions such that (1) i~utomatically generate the VHDL components appropriate for the proposed FLC architecture from the various design parameters (2) simulate the generated VHDL code on the Synopsys's VHDL Simulator, (3) automatically compiler, (4) generate the optimized, placed, and routed rawbit files from the synthesized modules by Xilinx's XactStep 6.0, (5) translate the rawbit files into the downloadable ex- [:cution reconfigurable FPGA board (VCC's EVCI), and (7) continuously monitor the control status graphically by communicating the FLC with the controlled target via S-bus. The developed FADIS is tested for its validity by carrying out the overall procedures of designing and implementing the FLC required for the truck-backer upper control, the reduction of control execution time due to the controller's FPGA implementation is verified by comparing with other implementations.

• The Journal of the Convergence on Culture Technology
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• v.6 no.3
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• pp.353-359
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• 2020

In this study, the controller structure and control algorithm of medical robot bed developed for pressure ulcer prevention and healing are described. The existing pressure ulcer prevention mattress is operated manually and the remaining maximum body pressure exceeds the pressure of ulcer generation, so there is always room for pressure ulcers. However, the system developed in this study does not generate the pressure ulcers because the body pressure drops to zero when the keyboard of the bed descends using the active electric driving keyboard. In addition, even if the bed is raised and the pressure above the critical body ulcer pressure is abnormal, the device and the control algorithm are designed so that the lasting time is within the pressure ulcer generation critical time and the pressure ulcer itself is not generated. The bed key board motor is a motor designed with the BLDC servos suitable for medical use and these can communicate each other easily through CAN(Car Area Network). The system is new medical robot bed that is effective in preventing pressure ulcers and will be distributed to many patients suffering from pressure ulcers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.28-37
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• 2010

In this paper, the IC (Integrated Circuit) for multi-channel asynchronous communication was designed by using FPGA and VHDL language. The existing chips for asynchronous communication that has been used commercially are composed of one to two channels. Therefore, when communication system with two channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 asynchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 256 bytes respectively and consequently high speed communication became possible. To detect errors between communications, it was designed with digital filter and check-sum logic and channel MUX logic so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. It was composed and simulated logic of VHDL described by using Cyclone II Series EP2C35F672C8 and QuartusII V8.1 of ALTERA company. In order to show the performance of designed IC, the test was conducted successfully in QuartusII simulation and experiment and the excellency was compared with TL16C550A of TI (Texas Instrument) company and ATmegal28 general-purpose micro controller of ATMEL company that are used widely as chips for asynchronous communication.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.144-155
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• 2013

This paper presents a low-cost remote power-quality-failure monitoring system (RPMS) using Android App and TI MCU (micro-controller unit), which is appliable to a micro-grid. The designed RPMS testbed consists of smart nodes, a server, and Android APPs. Especially, the C2000-series MCU-based RPMS smart node that is low-cost compared to existing monitoring systems has both a signal processing function for power signal processing and a data transmission function for power-quality monitoring data transmission. The signal processing function implements both a wavelet-based power failure detection algorithm including sag, swell, and interruption, and a FFT-based power failure detection algorithm including harmonics such that reliable and real-time power quality monitoring is guaranteed. The data transmission function implements a low-complexity RPMS transmission protocol and defines a simple data format (msg_Diag) for power monitoring message transmission. We may watch the monitoring data in real time both at a server and Android phone Apps connected to the WiFi network (or WAN). We use RS-232 (or Bluetooth) as the wired (or wireless) communication media between a server and nodes. We program the RPMS power-quality-failure monitoring algorithm using C language in the CCS (Code Composer Studio) 3.3 environment.

• Journal of Korea Game Society
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• v.7 no.3
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• pp.67-76
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• 2007

As the performance of game consoles is so highly progressed that services such as internet browsing become available on the consoles, the need for text input schemes on game consoles is rapidly raised. In this paper, we present a text input method of alphabet characters and several symbols using a gamepad, which is a widely used input device for most game consoles. Just like other text input methods using gamepad, our method allows users to enter texts by manipulating the gamepad with a user interface displayed on the screen of the console. A key idea of this paper is to present the user interface that is similar to the $4{\times}3$ keypad on mobile phones. The motivation of this idea is a principle that the experience of using a text input tool can be transferred to another tool that has similar interface. Another motivation is that the keyboard-based interface is too complex to be easily manipulated by simple input from a keypad, which is four orthogonal directions and several fire signals. Since most of keys on keypad of $4{\times}3$ keys are represented by a combination of two orthogonal directions, users feel easier in entering texts using keypad-based interface. We prove this argument in this paper by a user test of ten subjects. After about two experiment sessions, subjects reach 13 WPM in average, which proves that the proposed text input method enables much faster text input than the existing keyboard-based text input methods.

• Journal of KIISE:Information Networking
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• v.30 no.5
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• pp.656-667
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• 2003

Congestion control is a key task in reliable multicast along with error control. However, existing tree-based congestion control schemes such as MTCP and TRAMCC are designed for one-to-many reliable multicast and have some drawbacks when they are used for many-to-many reliable multicast. We propose an efficient congestion control mechanism, TMRCC, for tree-based many-to-many reliable multicast protocols. The proposed scheme is based on the congestion windowing mechanism and a rate controller is used in addition. The feedback for error recovery is exploited for congestion control as well to minimize the overhead at the receivers. The ACK timer and the NACK timers are set dynamically reflecting the network condition changes. The rate regulation algorithm in the proposed scheme is designed to help the flows sharing the same link to achieve the fair share quickly The performance of the proposed scheme is evaluated using ns-2. The simulation results show that the proposed scheme outperforms TRAMCC in terms of intra- session fairness and shows good level of responsiveness, TCP-friendliness, and scalability. In addition, we implemented the proposed scheme by integrating with GAM that is one of many-to-many reliable multicast protocols and evaluated the performance in a laboratory-wide testbed.