• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1045-1048
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• 2003

In this paper, we studied plasma damage of MIS capacitor with $Al_2$O$_3$ dielectric film. Using capacitor pattern with the same area but different perimeters, we tried to separate etching damage mechanism and to optimize the dry etching process. After etching both metal and dielectric layer by the same condition, leakage current and C-V measurements were carried out for Pt/A1$_2$O$_3$/Si structures. The flatband voltage shift was appeared in the C-V plot, and it was caused by the variation of the fixed interface charge and the interface trapped charge. From I-V measurement, it was found the leakage current along the periphery could not be ignored. Finally, we established the process condition of RF power 300W, 100mTorr, Ar/Cl$_2$ gas 60sccm as an optimal etching condition.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.375-378
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• 2002

We investigated the reduction of etching damage by additive O$_2$ in etching gas and recovery of etching damage by O$_2$ annealing. The PZT thin films were etched using additive Ar or O$_2$ into Cl$_2$/CF$_4$ gas mixing ratio of 8/2. In order to recover ferroelectric properties of PZT thin films after etching, the etched PZT thin films were annealed at 600 C in O$_2$ atmosphere for 10 min. The remanent polarization is decreased seriously and fatigue is accelerated in the PZT sample etched in Ar/(C1$_2$+CF$_4$) plasma, whereas these characteristics are improved in O$_2$/(Cl$_2$/CF$_4$). From x-ray photoelectron spectroscopy (XPS) analysis, the intensities of Pb-O, Zr-O and Ti-O peaks are changed and the etch byproducts such as metal chloride and metal fluoride are reduced by O$_2$ annealing. From electron probe micro analyzer (EPMA) and auger electron spectroscopy(AES), O$_2$ vacancy is observed after etching. In x-ray diffraction (XRD), the structure damage in the additive O$_2$ into C1$_2$/CF$_4$ is reduced and the improvement of ferroelectric behavioral annealed sample is consistent with the increase of the (100) and (200) PZT peaks.

• Journal of Sensor Science and Technology
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• v.24 no.1
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• pp.10-14
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• 2015

This paper reports the results of a study on the optimization of the etching profile, which is an important factor in deep-reactive-ion etching (DRIE), i.e., dry etching. Dry etching is the key processing step necessary for the development of the Internet of Things (IoT) and various microelectromechanical sensors (MEMS). Large-area etching (open area > 20%) under a high-frequency (HF) condition with nonoptimized processing parameters results in damage to the etched sidewall. Therefore, in this study, optimization was performed under a low-frequency (LF) condition. The HF method, which is typically used for through-silicon via (TSV) technology, applies a high etch rate and cannot be easily adapted to processes sensitive to sidewall damage. The optimal etching profile was determined by controlling various parameters for the DRIE of a large Si wafer area (open area > 20%). The optimal processing condition was derived after establishing the correlations of etch rate, uniformity, and sidewall damage on a 6-in Si wafer to the parameters of coil power, run pressure, platen power for passivation etching, and $SF_6$ gas flow rate. The processing-parameter-dependent results of the experiments performed for optimization of the etching profile in terms of etch rate, uniformity, and sidewall damage in the case of large Si area etching can be summarized as follows. When LF is applied, the platen power, coil power, and $SF_6$ should be low, whereas the run pressure has little effect on the etching performance. Under the optimal LF condition of 380 Hz, the platen power, coil power, and $SF_6$ were set at 115W, 3500W, and 700 sccm, respectively. In addition, the aforementioned standard recipe was applied as follows: run pressure of 4 Pa, $C_4F_8$ content of 400 sccm, and a gas exchange interval of $SF_6/C_4F_8=2s/3s$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.19-20
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• 2006

Two methods that can reduce reflectance in solar cells are surface texturing and anti-reflection coating. Wet chemical etching is a typical method that surface texturing of multi-crystalline silicon. Wet chemical etching methods are the acid texturization of saw damage on the surface of multi-crystalline silicon or double-step chemical etching after KOH saw damage removal too. These methods of surface texturing are realized by chemical etching in acid solutions HF-$HNO_3$-$H_2O$. In this solutions we can reduce reflectance spectra by simple process etching of multi-crystalline silicon surface. We have obtained reflectance of 27.19% m 400~1100nm from acidic chemical etching after KOH saw damage removal. This result is about 7% less than just saw damage removal substrate. The surface morphology observed by microscope and scanning electron microscopy (SEM).

• Journal of the Semiconductor & Display Technology
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• v.18 no.4
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• pp.35-39
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• 2019

Effect of Ge₂Sb₂Te₅ (GST) chalcogen composition on plasma induced damage was investigated by using Ar ions and F radicals. Experiments were carried out with three different modes; the physical etching, the chemical etching, and the ion-enhanced chemical etching mode. For the physical etching by Ar ions, the sputtering yield was obtained according to ion bombarding energy and there was no change in GST composition ratio. In the plasma mode, the lowest etch rate was measured at the same applied power and there was also no plasma induced damage. In the ion-enhanced chemical etching conditions irradiated with high energy ions and F halogen radicals, the GST composition ratio was changed according to the density of F radicals, resulting in higher roughness of the etched surface. The change of GST composition ratio in halogen plasma is caused by the volatility difference of GST-halogen compounds with high energy ions over than the activation energy of surface reactions.

• Transactions on Electrical and Electronic Materials
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• v.6 no.3
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• pp.87-90
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• 2005

$SiO_2$ via-hole etching with a high aspect ratio is a key process in fabricating ULSI devices; however, accumulated charge during plasma etching can cause etching stop, micro-loading effects, and charge build-up damage. To alleviate this concern, charge-up damage sensor was fabricated for the ultimate goal of real-time monitoring of accumulated charge. As an effort to reach the ultimate goal, fabricated sensor was used for electrical potential measurements of via holes between two poly-Si electrodes and roughly characterized under various plasma conditions using statistical design of experiment (DOE). The successful identification of potential difference under various plasma conditions not only supports the evidence of potential charge-up damage, but also leads the direction of future study.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.584-584
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• 2012

결정형 실리콘 태양전지 공정 중 표면 texturing 공정은 표면에 요철을 형성시켜 반사되는 빛 손실을 줄여서, 증가된 빛 흡수 양에 의해 단락전류(Isc)를 증가시키는데 그 목적이 있다. 표면 texturing 공정은 습식 식각과 건식 식각에 의한 방법으로 나눌 수 있다. 습식 식각은 KOH, TMAH, HNA 등의 실리콘 식각 용액을 사용하여 공정상의 위험도가 크고, 사용 후 용액의 폐기물에 의한 환경오염 문제가 있다. 건식 식각은 습식 식각과 달리 폐기물의 처리가 없고 미량의 가스를 이용한다. 그리고 다결정 실리콘 웨이퍼처럼 불규칙적인 결정방향에도 영향을 받지 않는 장점을 가지고 있어서 건식 식각을 이용한 표면 texturing 공정에 관한 많은 연구가 진행되고 있으며, 특히 RIE(reactive ion etching)를 이용한 태양전지 texturing 공정이 가장 주목을 받고 있다. 하지만 기존의 RIE를 이용하여 표면 texturing 공정을 하게 되면 500 nm 이하의 needle-like 구조의 표면이 만들어진다. Needle-like 구조의 표면은 전극을 형성할 때에 접촉 면적이 좁기 때문에 adhesion이 좋지 않은 것과 단파장 대역에서 광 손실이 많다는 단점이 있다. 본 논문에서는 기존의 RIE texturing의 단점을 보완하기 위해 챔버 내부에 metal-mesh를 장착한 후 RIE를 이용하여 $1{\mu}m$의 피라미드 구조를 형성하였고, RIE 공정 시 ion bombardment에 의한 표면 손상을 제거(RIE damage remove etching)하기 위하여 10초간 TMAH(Tetramethyl -ammonium hydroxide, 25 %) 식각 공정을 하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.244.2-244.2
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• 2013

Contact Pattern을 Plasma Etching을 통해 Pattering 공정을 진행함에 있어서 Plasma 내에 존재하는 High Energy Ion 들의 Bombardment 에 의해, Contact Bottom 의 Silicon Lattice Atom 들은 Physical 한 Damage를 받아 Electron 의 흐름을 방해하게 되어, Resistance를 증가시키게 된다. 또한 Etchant 로 사용되는 Fluorine 과 Chlorine Atom 들은, Contact Bottom 에 Contamination 으로 작용하게 되어, 후속 Contact 공정을 진행하면서 증착되는 Ti 나 Co Layer 와 Si 이 반응하는 것을 방해하여 Ohmic Contact을 형성하기 위한 Silicide Layer를 형성하지 못하도록 만든다. High Aspect Ratio Contact (HARC) Etching 을 진행하면서 Contact Profile을 Vertical 하게 형성하기 위하여 Bias Power를 증가하여 사용하게 되는데, 이로부터 Contact Bottom에서 발생하는 Etchant 로 인한 Damage 는 더욱 더 증가하게 된다. 이 Damage Layer를 추가적인 Secondary Damage 없이 제거하기 위하여 본 연구에서는 원자층 식각방법(Atomic Layer Etching Technique)을 사용하였다. 실험에 사용된 원자층 식각방법을 이용하여, Damage 가 발생한 Si Layer를 Secondary Damage 없이 효과적으로 Control 하여 제거할 수 있음을 확인하였으며, 30 nm Deep Contact Bottom 에서 Damage 가 제거될 수 있음을 확인하였다. XPS 와 Depth SIMS Data를 이용하여 상기 실험 결과를 확인하였으며, SEM Profile 분석을 통하여, Damage 제거 결과 및 Profile 변화 여부를 확인하였으며, 4 Point Prove 결과를 통하여 결과적으로 Resistance 가 개선되는 결과를 얻을 수 있었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.7
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• pp.551-556
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• 2001

In this work, the recovery of etching damage in the etched PZT thin film with $O_2$ annealing has been studied. The PZT thin films were etched as a function of Cl$_2$/Ar and additive CF$_4$ into Cl$_2$(80%) /Ar(20%). the etch rates of PZT thin films were 1600$\AA$/min at Cl$_2$(80%)/Ar(20%) and 1970 $\AA$/min at 30% additive Cf$_4$ into Cl$_2$(80%)/Ar(20%). In order to recover the characteristics of etched PZT thin films, the etched PZT thin films were annealed in $O_2$ atmosphere at various temperatures. From the hysteresis curves, ferroelectrical properties are improved by $O_2$ annealing process. The improvement of ferroelectric behavior is consistent with the increase of the (100) and (200) PZT phase revealed by x-ray diffraction (XRD). From x-ray photoelectron spectroscopy (XPS) analysis, intensities of Pb-O, Zr-O and Ti-O peak increase and the chemical residue peak is reduced by $O_2$ annealing. From the atomic force microscopy (AFM) images. it shows that the surface morphology of re-annealed PZT thin films after etching is improved.

• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.77-81
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• 2020

Silicon wafer etching in micro electro mechanical systems (MEMS) fabrication is challenging to form 3-D structures. Well known Si-wet etch of silicon employs potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) and sodium hydroxide (NaOH). However, the existing silicon wet etching process has a fatal disadvantage that etching of the back side of the wafer is hard to avoid. In this study, a wet etching bath for 150 mm wafers was designed to prevent back-side etching of silicon wafer, and we demonstrated the optimized process recipe to have anisotropic wet etching of silicon wafer without any damage on the backside. We also presented the design of wet bath for 300 mm wafer processing as a promising process development.