• ETRI Journal
• /
• 제36권4호
• /
• pp.617-624
• /
• 2014

Through-silicon via (TSV) technology provides much of the benefits seen in advanced packaging, such as three-dimensional integrated circuits and 3D packaging, with shorter interconnection paths for homo- and heterogeneous device integration. In TSV, a destructive cross-sectional analysis of an image from a scanning electron microscope is the most frequently used method for quality control purposes. We propose a quantitative evaluation method for TSV etch profiles whereby we consider sidewall angle, curvature profile, undercut, and scallop. A weighted sum of the four evaluated parameters, nominally total score (TS), is suggested for the numerical evaluation of an individual TSV profile. Uniformity, defined by the ratio of the standard deviation and average of the parameters that comprise TS, is suggested for the evaluation of wafer-to-wafer variation in volume manufacturing.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
• /
• pp.181-184
• /
• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STD structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters. we studied the correlation between CMP thickness of STI using high selectivity slurry. DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased. the N-poly foot is deteriorated. and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point,, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by $100\AA$. 3.2 $u\AA$ of IDSN is getting better in base 1 condition. In POE 50% condition. 1.7 $u\AA$ is improved. and 0.7 $u\AA$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2001년도 추계학술대회 논문집
• /
• pp.181-184
• /
• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• 한국지능시스템학회:학술대회논문집
• /
• 한국퍼지및지능시스템학회 2003년도 ISIS 2003
• /
• pp.599-602
• /
• 2003

A new technique is presented to construct predictive models of plasma etch processes. This was accomplished by combining a backpropagation neural network (BPNN) and a random generator (RC). The RG played a critical role to control neuron gradients in the hidden layer, The predictive model constructed in this way is referred to as a randomized BPNN (RG-BPNN). The proposed scheme was evaluated with a set of experimental plasma etch process data. The etch process was characterized by a 2$^3$ full factorial experiment. The etch responses modeled are 4, including aluminum (Al) etch rate, profile angle, Al selectivity, and do bias. Additional test data were prepared to evaluate model appropriateness. The performance of RC-BPNN was evaluated as a function of the number of hidden neurons and the range of gradient. for given range and hidden neurons, 100 sets of random neuron gradients were generated and among them one best set was selected for evaluation. Compared to the conventional BPNN, the proposed RC-BPNN demonstrated about 50％ improvements in all comparisons. This illustrates that the RG-BPNN of multi-valued gradients is an effective way to considerably improve the predictive ability of current BPNN of single-valued gradient.

• 반도체디스플레이기술학회지
• /
• 제5권2호
• /
• pp.47-49
• /
• 2006

Various methods of making thin film is being used in semiconductor manufacturing process. The most common method in this field includes CVD(Chemical Vapor Deposition) and PVD(Physical Vapor Deposition). Thin film is deposited on both the backside and the frontside of wafers. The thin film deposited on the backside has poor thickness profile, and can contaminate wafers in the following processes. If wafers with the thin film remaining on the backside are immersed in batch type process tank, the thin film fall apart from the backside and contaminate the nearest wafer. Thus, it is necessary to etch the backside of the wafer selectively without etching the frontside, and chemical injection nozzle positioned under the wafer can perform the backside etching. In this study, the backside chemical injection nozzle with optimized chemical injection profile is built for single wafer tool. The evaluation of this nozzle, performed on $Si_3N_4$ layer deposited on the backside of the wafer, shows the etching rate uniformity of less than 5% at the etching rate of more than $1000{\AA}$.