• Title/Summary/Keyword: error detecting code

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A Study on Joint Coding System using VF Arithmetic Code and BCH code

  • Sukhee Cho;Park, Jihwan;Ryuji Kohno
    • Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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    • 1998.12a
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    • pp.537-545
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    • 1998
  • This paper is the research about a joint coding system of source and channel coding using VF(Variable-to-fixed length) arithmetic code and BCH code. We propose a VF arithmetic coding method with EDC( Error Detecting Capability) and a joint coding method in that the VF arithmetic coding method with EDC is combined with BCH code. By combining both the VF arithmetic code with EDC and BCH code. the proposed joint coding method corrects a source codeword with t-errors in decoding of BCH code and carries out a improvement of the EDC of a codeword with more than (t+1)-errors in decoding of the VF arithmetic coding with EDC. We examine the performance of the proposed method in terms of compression ratio and EDC.

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AN UPPER BOUND ON THE NUMBER OF PARITY CHECKS FOR BURST ERROR DETECTION AND CORRECTION IN EUCLIDEAN CODES

  • Jain, Sapna;Lee, Ki-Suk
    • Journal of the Korean Mathematical Society
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    • v.46 no.5
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    • pp.967-977
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    • 2009
  • There are three standard weight functions on a linear code viz. Hamming weight, Lee weight, and Euclidean weight. Euclidean weight function is useful in connection with the lattice constructions [2] where the minimum norm of vectors in the lattice is related to the minimum Euclidean weight of the code. In this paper, we obtain an upper bound over the number of parity check digits for Euclidean weight codes detecting and correcting burst errors.

Performance Analysis of the Hybrid ARQ System Using Hamming Codes (해밍코드를 이용한 효율적인 Hybrid ARQ 시스템의 성능분석)

  • 박성경;김신영;강창언
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.13 no.6
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    • pp.535-544
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    • 1988
  • In this paper, the hybrid ARQ scheme, which is incorporated the selective-repeat ARQ system with the finite receiver buffer and the single-error-correcting and double-error-detecting(63.56) cyclic Hamming code system, has been investigated. As a result of simulation, the proposed hybrid ARQ scheme shows that that throughput efficiencies are improved by one error correction, and that the reversed codewords due to retransmission are delivered to the user in order by means of detecting two errors. The hybrid ARQ scheme significantly outperforms the FEC or the ideal selective-repeat ARQ system in the respect of throughput and reliability, especially when the channel error rate is approximately in the range from $10^{-2}$~$10^{-3}$.

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FPGA implementation of overhead reduction algorithm for interspersed redundancy bits using EEDC

  • Kim, Hi-Seok
    • Journal of IKEEE
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    • v.21 no.2
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    • pp.130-135
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    • 2017
  • Normally, in data transmission, extra parity bits are added to the input message which were derived from its input and a pre-defined algorithm. The same algorithm is used by the receiver to check the consistency of the delivered information, to determine if it is corrupted or not. It recovers and compares the received information, to provide matching and correcting the corrupted transmitted bits if there is any. This paper aims the following objectives: to use an alternative error detection-correction method, to lessens both the fixed number of the required redundancy bits 'r' in cyclic redundancy checking (CRC) because of the required polynomial generator and the overhead of interspersing the r in Hamming code. The experimental results were synthesized using Xilinx Virtex-5 FPGA and showed a significant increase in both the transmission rate and detection of random errors. Moreover, this proposal can be a better option for detecting and correcting errors.

Effects of LDPC Code on the BER Performance of MPSK System with Imperfect Receiver Components over Rician Channels

  • Djordjevic, Goran T.;Djordjevic, Ivan B.;Ivanis, Predrag N.
    • ETRI Journal
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    • v.31 no.5
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    • pp.619-621
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    • 2009
  • In this letter, we study the influence of receiver imperfections on bit error rate (BER) degradations in detecting low-density parity-check coded multilevel phase-shift keying signals transmitted over a Rician fading channel. Based on the analytical system model which we previously developed using Monte Carlo simulations, we determine the BER degradations caused by the simultaneous influences of stochastic phase error, quadrature error, in-phase-quadrature mismatch, and the fading severity.

Security Verification of Video Telephony System Implemented on the DM6446 DaVinci Processor

  • Ghimire, Deepak;Kim, Joon-Cheol;Lee, Joon-Whoan
    • International Journal of Contents
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    • v.8 no.1
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    • pp.16-22
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    • 2012
  • In this paper we propose a method for verifying video in a video telephony system implemented in DM6446 DaVinci Processor. Each frame is categorized either error free frame or error frame depending on the predefined criteria. Human face is chosen as a basic means for authenticating the video frame. Skin color based algorithm is implemented for detecting the face in the video frame. The video frame is classified as error free frame if there is single face object with clear view of facial features (eyes, nose, mouth etc.) and the background of the image frame is not different then the predefined background, otherwise it will be classified as error frame. We also implemented the image histogram based NCC (Normalized Cross Correlation) comparison for video verification to speed up the system. The experimental result shows that the system is able to classify frames with 90.83% of accuracy.

Compiler triggered C level error check (컴파일러에 의한 C레벨 에러 체크)

  • Zheng, Zhiwen;Youn, Jong-Hee M.;Lee, Jong-Won;Paek, Yun-Heung
    • The KIPS Transactions:PartA
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    • v.18A no.3
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    • pp.109-114
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    • 2011
  • We describe a technique for automatically proving compiler optimizations sound, meaning that their transformations are always semantics-preserving. As is well known, IR (Intermediate Representation) optimization is an important step in a compiler backend. But unfortunately, it is difficult to detect and debug the IR optimization errors for compiler developers. So, we introduce a C level error check system for detecting the correctness of these IR transformation techniques. In our system, we first create an IR-to-C converter to translate IR to C code before and after each compiler optimization phase, respectively, since our technique is based on the Memory Comparison-based Clone(MeCC) detector which is a tool of detecting semantic equivalency in C level. MeCC accepts only C codes as its input and it uses a path-sensitive semantic-based static analyzer to estimate the memory states at exit point of each procedure, and compares memory states to determine whether the procedures are equal or not. But MeCC cannot guarantee two semantic-equivalency codes always have 100% similarity or two codes with different semantics does not get the result of 100% similarity. To increase the reliability of the results, we describe a technique which comprises how to generate C codes in IR-to-C transformation phase and how to send the optimization information to MeCC to avoid the occurrence of these unexpected problems. Our methodology is illustrated by three familiar optimizations, dead code elimination, instruction scheduling and common sub-expression elimination and our experimental results show that the C level error check system is highly reliable.

A Low Power ECC H-matrix Optimization Method using an Ant Colony Optimization (ACO를 이용한 저전력 ECC H-매트릭스 최적화 방안)

  • Lee, Dae-Yeal;Yang, Myung-Hoon;Kim, Yong-Joon;Park, Young-Kyu;Yoon, Hyun-Jun;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.1
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    • pp.43-49
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    • 2008
  • In this paper, a method using the Ant Colony Optimization(ACO) is proposed for reducing the power consumption of memory ECC checker circuitry which provide Single-Error Correcting and Double-Error Detecting(SEC-DED). The H-matrix which is used to generate SEC-DED codes is optimized to provide the minimum switching activity with little to no impact on area or delay using the symmetric property and degrees of freedom in constructing H-matrix of Hsiao codes. Experiments demonstrate that the proposed method can provide further reduction of power consumption compared with the previous works.

A Study on Performance Enhancement for Iris Recognition by Eyelash Detection (속눈썹 추출 방법을 이용한 홍채 인식 성능 향상 연구)

  • Kang Byung Joon;Park Kang Ryoung
    • The KIPS Transactions:PartB
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    • v.12B no.3 s.99
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    • pp.233-238
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    • 2005
  • With iris recognition algorithm, unique iris code can be generated and user can be identified by using iris pattern. However, if unnecessary information such as eyelash is included in iris region, the error for iris recognition is increased, consequently. In detail, if iris region is used to generate ins code not excluding eyelash and the position of eyelash is moved, the iris codes are also changed and the error rate is increased. To overcome such problem, we propose the method of detecting eyelash by using mask and excluding the detected eyelash region in case of generating iris code. Experimental results show that EER(Equal Error Rate) for iris recognition using the proposed algorithm is lessened as much as $0.18\%$ compared to that not using it.

A Morphology Technique-Based Boundary Detection in a Two-Dimensional QR Code (2차원 QR코드에서 모폴로지 기반의 경계선 검출 방법)

  • Park, Kwang Wook;Lee, Jong Yun
    • Journal of Digital Convergence
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    • v.13 no.2
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    • pp.159-175
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    • 2015
  • The two-dimensional QR code has advantages such as directional nature, enough data storage capacity, ability of error correction, and ability of data restoration. There are two major issues like speed and correctiveness of recognition in the two-dimensional QR code. Therefore, this paper proposes a morphology-based algorithm of detecting the interest region of a barcode. Our research contents can be summarized as follows. First, the interest region of a barcode image was detected by close operations in morphology. Second, after that, the boundary of the barcode are detected by intersecting four cross line outside in a code. Three, the projected image is then rectified into a two-dimensional barcode in a square shape by the reverse-perspective transform. In result, it shows that our detection and recognition rates for the barcode image is also 97.20% and 94.80%, respectively and that outperforms than previous methods in various illumination and distorted image environments.