• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.768-771
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• 2007

Recently, Nand flash memory is widely used for digital equipments and its capacity and performance are rapidly improving. The limit on the number of writings and readings to/from Nand flash memory does not guarantee the integrity of its data. Therefore, ECC algorithm should be applied to the Nand flash controller. To reduce the access time, we use the look-up table to implement the ECC algorithm instead of the conventional logic gates.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.648-651
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• 2001

This paper describes the 8-error-correction (204, 188) Reed-Solomon Decode. over GF(2$^{8}$ ) for a satellite communication. It is synthsized using a CMOS library. Decoding algorithm of Reed-Solomon codes consists of four steps which are to compute syndromes, to find error-location polynomial, to decide error-location, and to slove error-values. The decoder is designed using Modified Euclid algorithm in this paper. First of all, The functionalities of the circuit are verified through C++ programs, and then it is designed in Verilog HDL. It is verified through the logic simulations of each blocks. Finally, The Reed-Solomon Decoder is synthesized with Synopsys Tool.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.13 no.1
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• pp.39-49
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• 2013

This paper presents a method of improving the performance of a day-ahead 24-h load curve and peak load forecasting. The next-day load curve is forecasted using radial basis function (RBF) neural network models built using the best design parameters. To improve the forecasting accuracy, the load curve forecasted using the RBF network models is corrected by the weighted sum of both the error of the current prediction and the change in the errors between the current and the previous prediction. The optimal weights (called "gains" in the error correction) are identified by differential evolution. The peak load forecasted by the RBF network models is also corrected by combining the load curve outputs of the RBF models by linear addition with 24 coefficients. The optimal coefficients for reducing both the forecasting mean absolute percent error (MAPE) and the sum of errors are also identified using differential evolution. The proposed models are trained and tested using four years of hourly load data obtained from the Korea Power Exchange. Simulation results reveal satisfactory forecasts: 1.230% MAPE for daily peak load and 1.128% MAPE for daily load curve.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1575-1582
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• 1998

Reed-Solomon(RS) code which is especially effective against burst error is studied as a forward error correction technique in this ppaer. The circuits of RS encoder and decoder for ASIC implementation are designed and presented employing modified Euclid's algorithm. The functionalities of the designed circuits are verified though C programs which simulates the circuits over the various errors and erasures. The pipelined circuits using systolic arrays are designed for ASIC realization in VHDL, and verified through the logic simulations. Finally the circuit synthesis of RS encoder and decoder can be achieved.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.11 no.4
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• pp.286-292
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• 2011

Biometrics systems are used in a wide range of areas, including the area of crime prevention, due to their unique characteristics. However, serious problems can occur if biometric information is disclosed to an unauthorized user. To address these issues, this paper proposes a real valued fuzzy vault method, which adopts a real number error correction code to implement a fuzzy vault scheme for protecting fingerprint temples. The proposed method provides the benefit of allowing the private key value to be changed at any time, unlike biometric template such as a fingerprint, which is not easily renewable even if its security has been breached. The validity of the proposed method is verified for fingerprint verification.

• 한국정보통신설비학회:학술대회논문집
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• 2002.08a
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• pp.27-30
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• 2002

10-bit 해상도, 10MS/s의 ADC를 Stage 당 1.5-Bit의 Resolution을 가지는 Redundant signed digit(RSD) 방식의 파이프라인 구조를 이용하여 설계하였다. Error Correction Logic을 사용함으로써 비교기를 Coarse하게 설계하였고 잔류 전압 증폭기의 최적 Scaling을 통하여 일반적인 ADC에 비해 성능 저하 없이 효율적으로 소비 전력을 감소시켰다. 또한, Charge Pump의 선택적 사용을 통해 기생 커패시턴스의 영향을 최소화함으로써 잔류전압 증폭기의 출력 전압 특성을 향상 시켰다. 삼성 0.35u CMOS 공정 파라미터를 이용하여 입력 전압 $-1{\sim}1V$, 공급 전압 $-1.5{\sim}1.5V$에서 18.73mW로 설계하였으며 HSPICE로 시뮬레이션 하였다.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.975-978
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• 2003

본 논문에서는 비디오 신호 인터페이스를 위해 10비트 50MHz ADC 를 설계하였으며 DCL(digital-error correction logic)을 갖는 3-3-3-4 구조의 파이프라인 방식을 사용하였다. SHA(sample and hold amplifier)와 MDAC (multiplying digital-to-analog converter)에 쓰이는 증폭기는 높은 이득을 갖도록 gain-boosting 기법을 적용하였으며, 전력소모와 면적을 줄이기 위해 capacitor scaling 기법을 적용하였다. 본 ADC 는 0.35 μm double-poly four-metal n-well CMOS 공정으로 설계 및 제작하였으며, 전체 회로는 3.3V 단일 전원 전압에서 동작하도록 설계하였다. 측정 결과 5MHz 의 입력을 인가하였을 때 SNDR 은 56.7dB, 전체 전력 소모는 112mW 이며, 입출력 단의 패드를 포함한 전체 칩 면적은 2.6mm×2.6mm이다.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3199-3201
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• 1999

Convolutional coding with Viterbi decoding is known as a powerful method for forward error correction among many kinds of channel coding methods. This paper presents a soft decision Viterbi decoder which has systolic array trace-back architecture[1]. Soft decision is known as more effective method than hard decision and most of digital communication systems use soft decision. The advantage of using a systolic array decoder is that the trace-back operation can be accomplished continuously in an array of registers in a pipe-line fashion, instead of waiting for the entire trace-back procedure to be completed at each iteration. Therefore it may be suitable for faster communication system. We described operations of each module of the decoder and showed results of the logic synthesis and functional simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.485-488
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• 2009

The class of BCH codes is a large class of error correction codes. HDL implementation of BCH code generator to change code rate. and used System Generator, and implemented hardware to FPGA. Loaded bit stream to a FPGA board in order to verify this design to Hardware co-simulation from these results. Also, compared as investigated the maximum action frequency through timing analysis and resource of logic in order to evaluate performance of BCH code generator.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.7
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• pp.1579-1588
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• 2014

The LAN method is the most widely used in domestic high-speed internet access and rapidly moving to 1 Gbps Ethernet from 100 Mbps one to provide high-speed services such as UHD TV. The 1000BASE-T PHY with 4 pairs UTP transmits a PAM-5 signal at the 125 MHz clock per each pair to achieve 1 Gbps rate. In order to correct errors over the channel, the transmitter uses a TCM which is combined the convolutional encoder and PAM-5, and the receiver uses the Viterbi decoder. In this paper, we implement a Viterbi decoder which can correct two pair errors and operate at the least 125 MHz clock speed. Finally, we will verify the error correction function and the operating speed of the implemented decoder with a logic analyzer.