• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.27-32
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• 2022

RISC-V is an open instruction set architecture (ISA) developed in 2010 at UC Berkeley, and active research is being conducted as a processor to compete with ARM. In this paper, we propose an SoC system including an RV32I ISA-based 32-bit 5-stage pipeline processor and AHB bus master. The proposed RISC-V processor supports 37 instructions, excluding FENCE, ECALL, and EBREAK instructions, out of a total of 40 instructions based on RV32I ISA. In addition, the RISC-V processor can be connected to peripheral devices such as BRAM, UART, and TIMER using the AHB-lite bus protocol through the proposed AHB bus master. The proposed SoC system was implemented in Arty A7-35T FPGA with 1,959 LUTs and 1,982 flip-flops. Furthermore, the proposed hardware has a maximum operating frequency of 50 MHz. In the Dhrystone benchmark, the proposed processor performance was confirmed to be 0.48 DMIPS.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.74-84
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• 2000

This paper deals with procedures for design and implementation of a DSP, which is compatible with TMS320C30 DSP. CBS(Cycle Based Simulator) is developed to study the architecture of the target DSP. The simulator gives us detailed information such as function block operation, control signal values, register condition, bus and memory values when a instruction is being carried out. RTL design is carried out by VHDL. Logic simulation and hardware emulation are employed to verify proper operation of the design. The DSP is fabricated with 0.6${\mu}m$ CMOS technology. The Chip has 450,000 gates complexity, $9{\times}9mm^2$ area, 20 MIPS operation speed. It is confirmed by running 109 instructions out of 114 instructions and 13 kinds of algorithm that the developed DSP has compatibility with TMS320C30.

• The KIPS Transactions:PartD
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• v.9D no.2
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• pp.289-296
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• 2002

The web, which is most actively used in the internet environment, is changing educational system. Students usually prefer the interactive and multimedia learning aids based on web applications and web media to static web pages. The former is known to enhance the effectiveness of learning. This paper proposes a study system which involves effective adaptation to the various changing factors of learners' progress and the corresponding automated evaluation system. Conventional evaluation utilizes normalized method, where the learning objectives generally set by the instructors or educational operators/administrators are usually pursued rather than the interest of the individual learners, which is not ideal for the computer-based learning. Web-based project-oriented learning system provokes the mutual participations among the users, operators, and administrators in understanding the jobs to be performed and the effort to enhance the progressive developments of knowledge and application capabilities. In this Paper, an automated evaluation system is implemented, where the instructors and web-operators/administrators work as hosts for education. The learners take advantage of user-oriented comparative learning and pattern design. The design and implementation of the project-oriented evaluation methods performed in the internet/intranet environments are discussed.

• Journal of Practical Engineering Education
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• v.12 no.2
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• pp.255-264
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• 2020

In the database design course, the team project is a very important process to develop students' database design competencies. In order to carry out team projects smoothly, active interaction between students and the professor as well as collaboration among team members are very important. However, a full uncontacted class was suddenly decides in the first semester of 2020, it was questionable whether it would be possible to effectively manage this course, where team projects to construct database take up a big portion. However team projects were able to proceed without major problems through interaction using real-time video media such as zoom, and discussions, quizzes, and Q&A supported by the online education support system (LMS), and online presentations, mutual evaluations, and so on. This paper shares the experience of managing engineering team projects in uncontacted classes and based on three surveys introduces desirable improving directions of this instruction and some suggestions to improve uncontacted classes overall.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.2
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• pp.100-107
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• 2011

As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements(PEs) and operates on a 3-stage pipelining. Experimental results for the JPEG encoding algorithm indicate that the proposed parallel processor outperforms conventional parallel processors in terms of performance and energy efficiency. In addition, the proposed parallel processor architecture was developed and verified with verilog HDL and a FPGA prototype system.

• Journal of Computing Science and Engineering
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• v.5 no.2
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• pp.121-130
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• 2011

Recent research indicates that transient errors will increasingly become a critical concern in microprocessor design. As embedded processors are widely used in reliability-critical or noisy environments, it is necessary to develop cost-effective fault-tolerant techniques to protect processors against transient errors. The register file is one of the critical components that can significantly affect microprocessor system reliability, since registers are typically accessed very frequently, and transient errors in registers can be easily propagated to functional units or the memory system, leading to silent data error (SDC) or system crash. This paper focuses on investigating the impact of register file soft errors on system reliability and developing cost-effective techniques to improve the register file immunity to soft errors. This paper proposes the register vulnerability factor (RVF) concept to characterize the probability that register transient errors can escape the register file and thus potentially affect system reliability. We propose an approach to compute the RVF based on register access patterns. In this paper, we also propose two compiler-directed techniques and a hybrid approach to improve register file reliability cost-effectively by lowering the RVF value. Our experiments indicate that on average, RVF can be reduced to 9.1% and 9.5% by the hyperblock-based instruction re-scheduling and the reliability-oriented register assignment respectively, which can potentially lower the reliability cost significantly, without sacrificing the register value integrity.

• Journal of Engineering Education Research
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• v.13 no.6
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• pp.152-163
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• 2010

Civil engineering based on construction and maintenance of infrastructures for social and human development, it has a conservative aspects to adopt the high-technology and pace of change from ancient society. Therefore, the education of civil engineering consists of very similar contents from the past until now. Also, civil engineering, area is established the infrastructure widely included structure, geotechnical, hydraulic, environmental, surveying, construction management. Civil engineering have totally difference characteristics compared to manufacturing industry field for market interests such as mechanical engineering, chemical engineering, material engineering etc. Therefore, the capstone design concepts of civil engineering for public interests must be changed and applied unlike any other engineering areas capstone design. In this paper, the modified capstone design contents and instruction in civil engineering of Yonsei University is informed and evaluated using undergraduate students' course evaluations and learning assessment to verify the efficiency of modified capstone design in civil engineering.

• The Journal of Korean Association of Computer Education
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• v.4 no.2
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• pp.115-123
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• 2001

In the early stage of Web-based Instruction, it didn't gain preference in spite of it's benefit of convenience. The main reason is, I think, the lack of generality at the education system which eventually results in unsatisfactory facilities compared with the requirement of teachers and students. And the early systems don't make good use of the plenty data in distributed environment, and don't show so good reliablity due to lack of systematic design and development. In this paper, we suggest WBI developing technology using the concept of WBSE. WBI developing is consist of component of pre-developed education software, integration of component using its reusability, and production of more requirement-satisfactory education software.

• International Journal of Internet, Broadcasting and Communication
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• v.16 no.3
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• pp.212-220
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• 2024

A recently the advancement of society, AI technology has made significant strides, especially in the fields of computer vision and voice recognition. This study introduces a system that leverages these technologies to recognize users through a camera and relay commands within a vehicle based on voice commands. The system uses the YOLO (You Only Look Once) machine learning algorithm, widely used for object and entity recognition, to identify specific users. For voice command recognition, a machine learning model based on spectrogram voice analysis is employed to identify specific commands. This design aims to enhance security and convenience by preventing unauthorized access to vehicles and IoT devices by anyone other than registered users. We converts camera input data into YOLO system inputs to determine if it is a person, Additionally, it collects voice data through a microphone embedded in the device or computer, converting it into time-domain spectrogram data to be used as input for the voice recognition machine learning system. The input camera image data and voice data undergo inference tasks through pre-trained models, enabling the recognition of simple commands within a limited space based on the inference results. This study demonstrates the feasibility of constructing a device management system within a confined space that enhances security and user convenience through a simple real-time system model. Finally our work aims to provide practical solutions in various application fields, such as smart homes and autonomous vehicles.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.1
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• pp.116-126
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• 2011

In this paper, we present a multi-media processor which can decode multiple-format video standards. The designed processor is evaluated with optimized MPEG-2, MPEG-4, and AVS (Audio video standard). There are two approaches for developing of real-time video decoders. First, hardware-based system is much superior to a processor-based one in execution time. However, it takes long time to implement and modify hardware systems. On the contrary, the software-based video codecs can be easily implemented and flexible, however, their performance is not so good for real-time applications. In this paper, in order to exploit benefits related to two approaches, we designed a processor called ASIP(Application specific instruction-set processor) for video decoding. In our work, we extracted eight common modules from various video decoders, and added several multimedia instructions to the processor. The developed processor for video decoders is evaluated with the Synopsys platform simulator and a FPGA board. In our experiment, we can achieve about 37% time saving in total decoding time.