• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.11
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• pp.4310-4319
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• 2010

In 21th century moving rapidly up to the knowledge and information society, creative problem-solving abilities are preferentially required to engineers. Though there may be various approaches to develop such abilities, PBL instruction method can be an effective alternative to develop such abilities. Recognizing this, one 'JPBL' model was constructed and introduced in this study. The model was developed independently based general existing PBL models and applied to university students to analyze its effectiveness in the aspect of class satisfaction and organizational commitment. Based on results, the meaning and limitation of the model development were discussed.

• Design & Manufacturing
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• v.16 no.3
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• pp.34-38
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• 2022

Regular expression pattern matching is widely used in applications such as computer virus vaccine, NIDS and DNA sequencing analysis. Hardware-based pattern matching is used when high-performance processing is required due to time constraints. ReCPU, SMPU, and REMP, which are processor-based regular expression matching processors, have been proposed to solve the problem of the hardware-based method that requires resynthesis whenever a pattern is updated. However, these processor-based regular expression matching processors inefficiently handle repetitive operations of regular expressions. In this paper, we propose a new instruction set to improve the inefficient repetitive operations of ReCPU and SMPU. We propose REMPi, a regular expression matching processor that enables efficient iterative operations based on the REMP instruction set. REMPi improves the inefficient method of processing a particularly short sub-pattern as a repeat operation OR, and enables processing with a single instruction. In addition, by using a down counter and a counter stack, nested iterative operations are also efficiently processed. REMPi was described with Verilog and synthesized on Intel Stratix IV FPGA.

• International Journal of Contents
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• v.5 no.2
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• pp.53-58
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• 2009

This paper presents a novel approach in the design of a CAM for an asynchronous cache. The architecture of cache mainly consists of four units: control logics, content addressable memory, completion signal logic units and instruction memory. The pseudo-DCVSL is useful to make a completion signal which is a reference for handshake control. The proposed CAM is a very simple extension of the basic circuitry that makes a completion signal based on DI model. The cache has 2.75KB CAM for 8KB instruction memory. We designed and simulated the proposed asynchronous cache including CAM. The results show that the cache hit ratio is up to 95% based on pseudo-LRU replacement policy.

• Journal of the Korean Society for Precision Engineering
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• v.1 no.2
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• pp.69-74
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• 1984

In this paper we present a microprocessor-based interpolator using algebraic arithmetic method. The interpolator consists of 2910 "bit-slice" microprocessor chips and 0.5K ROMs of microprogram memory. The system design is an instruction-data-based architecture with 250ns cycle time. A significant feature of the interpolator is that it has flexibility, very fast interpolatioon speed of (max) 250K pulses/sec, and performs additional functions simultaneously. Throughout the paper detailed explanations are given as to how one can design the hardware and software of the interpolator efficently. In addi- tion to hardware and software design, experimental results are pressented.ressented.

• The Journal of Korean Institute for Practical Engineering Education
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• v.3 no.2
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• pp.142-146
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• 2011

In this paper, to invigorate elderly-friendly industry, a case study on curriculum for re-educational work of the field engineers is introduced. The curriculum has been developed to retrain technicians and engineers in IT-based elderly-friendly business industry, to help them develop elderly-friendly products, and it have been evolved by operating it and analyzing outcome and satisfaction levels since August in 2009. The re-education work of the field engineers are designed for invigorating the IT-based elderly-friendly business industry, based on the instruction system design(ISD) model. To develop IT-based elderly-friendly products, the elderly-friendly accessible design and the elderly-friendly living and health care equipment design are required. For the elderly-friendly accessible design, it consists of "Elderly-Friendly Engineering Based on Human Characteristics", "Color Sensibility and Universal Design for The Elderly", and "Design Understanding and Process". For the elderly-friendly living and health care equipment design, it consists of "Embedded System Design and Debugging Experiments for Elderly-Friendly IT Equipment", "Elderly-Friendly Android Implementation Design", and "Design and Experiments of Silver-care Android-based Smart Equipment".

• Journal of IKEEE
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• v.12 no.2
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• pp.118-123
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• 2008

The Khronos group releases OpenGL ES 2.0 API specification bringing streamlined shader programming to graphics processor of embedded system. For this reason, the mobile devices have need of graphics processor for supporting a OpenGL ES 2.0 API. We need to extend instruction`s length to support OpenGLES 2.0 API, so it needs more memory size. In this paper, we propose a new instruction format that offers availability for use the instructions. This proposed instruction adopt a variable length method and unit instruction architecture. This proposed instruction architecture that support to OpenGLES 2.0 API has consist of 32bit unit instructions up to 4 which can be combined for embellishing each other. Therefore, it can execute flexible instruction combination and reduce waste of instruction fields.

• Journal of Engineering Education Research
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• v.17 no.2
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• pp.11-24
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• 2014

The purpose of this study is to develop a teaching-learning model of convergence project based on team teaching. Based on development research methodology which explored a university case, the teaching-learning model was developed including three phases such as preparation, planning, and implementation & evaluation. The preparation phase has three steps as follows: to organize team teaching faculty; to develop convergence projects cooperated by industry and university; and to design instructions based on supporting convergence projects. The last step of preparation phase consists of five design activities of: (1) instructions and teaching contents; (2) communication channel among faculty members; (3) feedback system on students' performance; (4) tools to support learners' activity; and (5) evaluation system. The planning phase has two steps to analyze learners and to introduce and modify instruction and themes of convergence projects. The implementation & evaluation phase includes five steps as bellow: (1) to organize project teams and match teams with faculty members; (2) to do team building and assign duties to students of a team; (3) to provide instruction and consulting to teams; (4) to help teams to conduct projects through creative problem solving; and (5) to design mid-term/final presentation and evaluation. Lastly, the research implications and limitations were discussed for future studies.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.3
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• pp.411-417
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• 2018

This paper proposes and implements an on-line instruction manual system which can generate the instruction manual page for the target device at the smartphone on the spot. The instruction manual app. on smartphone scans a QR code or reads NFC tag attached in the instruction manual management module embedded in the target device, and receives instruction manual data from the instruction manual management module through the Bluetooth communications and finally shows the refined instruction manual pages on the smartphone display using a Web-based templates. For the evaluation we embedded the instruction manual management module for an industrial generator with its instruction manual data. Assuming a circumstance of blackout we show that the proposed system can reduce the repair work within two steps compared to three steps in the existing one without the proposed system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.229-234
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• 2007

In this paper, we present an efficient instruction set architecture using vector register file hardware to accelerate operation of general matrix-vector operations in DSP microprocessor. The technique enables in-situ row-access as well as column access to the register files. It can reduce the number of memory access significantly. The technique is especially useful for block-based video signal processing kernels such as FFT/IFFT, DCT/IDCT, and two-dimensional filtering. We have applied the new instruction set architecture to in-loop deblocking filter processing in H.264 decoder. Performance comparisons show that the required load/store operations for the in-loop deblocking filter can be reduced about 42%. The architecture would improve the processing speed, and code density in DSP microprocessor especially for video signal processing substantially.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.4
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• pp.559-566
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• 2002

n this paper, we propose a WBI(Web Based Instruction) for individualized learning using push and pull technologies with WWW(World Wide Web). As well as push End pull technologies, the proposing system is implemented with JSP(Java Server Page) and JDBC(Java Database Connectivity) of java technologies based on the client/server envirionments for the purpose of providing practical lectures to students.