• Journal of the Korea Society of Computer and Information
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• v.19 no.10
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• pp.1-12
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• 2014

This paper implements and improves the performance of high computational subtractive clustering algorithm using a single instruction, multiple data (SIMD) based many-core processor. In addition, this paper implements five different processing element (PE) architectures (PEs=16, 64, 256, 1,024, 4,096) to select an optimal PE architecture for the subtractive clustering algorithm by estimating execution time and energy efficiency. Experimental results using two different medical images and three different resolutions ($128{\times}128$, $256{\times}256$, $512{\times}512$) show that PEs=4,096 achieves the highest performance and energy efficiency for all the cases.

• Journal of Advanced Navigation Technology
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• v.14 no.2
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• pp.233-238
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• 2010

In this paper, we applied the forward and backward error recovery techniques to a reduced instruction set computer (risc) processor to develop two fault-tolerant processors, namely, fetch redundant risc (FRR) processor and a redundancy execute risc (RER) processor. To evaluate the fault-tolerance capability of three target processors, we developed the base risc processor, FRR processor, and RER processor in SystemC hardware description language. We performed fault injection experiment using the three SystemC processor models and the SystemC-based simulation fault injection technique. From the experiments, for the 1-bit transient fault, the failure rate of the FRR, RER, and base risc processor were 1%, 2.8%, and 8.9%, respectively. For the 1-bit permanent fault, the failure rate of the FRR, RER, and base risc processor were 4.3%, 6.5%, and 41%, respectively. As a result, for 1-bit fault, we found that the FRR processor is more reliable among three processors.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.259-266
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM (or SRAM) cell. Layout pitch of one-bit-wide logic is Identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1) simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• Journal of Broadcast Engineering
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• v.16 no.4
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• pp.596-601
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• 2011

In this paper, we propose a fast depth-image-based rendering method to generate a virtual view image in real-time using a graphic processor unit (GPU) for a 3D broadcasting system. Before the transmission, we encode the input 2D+depth video using the H.264 coding standard. At the receiver, we decode the received bitstream and generate a stereo video using a GPU which can compute in parallel. In this paper, we apply a simple and efficient hole filling method to reduce the decoder complexity and reduce hole filling errors. Besides, we design a vertical parallel structure for a forward mapping process to take advantage of the single instruction multiple thread structure of GPU. We also utilize high speed GPU memories to boost the computation speed. As a result, we can generate virtual view images 15 times faster than the case of CPU-based processing.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1329-1337
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• 2008

The project of Education information is promoted to maximize the efficiency of Teaching-Learning at schools. So Ministry of Education & Human Resources Development develops and spreads the Computer Assisted Instruction(CAI) and outstanding Educational Software to help learners who can utilize this software and make learning environment to form their own recognition. As the number of this software is increased, the necessity of management of Educational Software is required. This study divides Educational Software into three kinds, teaching-learning software, business management software, and system management software, and suggests how to use these softwares effectively according to this division. After the users log into the system through joining members, they are divided into manager module, teachers module, and students module. The manager manages all software like registration, revision, reference of date and so on. The teacher accesses properly. The student accesses teaching-learning software and prepares and reviews his lessons at any time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11B
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• pp.1710-1714
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• 2010

The budget for the acquisition and R&D for the national defence systems has come out of tax payers' pockets. On the other hand, the weapon systems become more complex and thus the underlying costs tend to increase continuously. As such, the need for efficiently managing the budget has drastically increased. In accordance with this necessity, the Defence Acquisition Program Administration (DAPA) of Korea has issued the instruction No.65 dictating that systems engineering (SE) must be applied when weapon systems are acquired or developed in Korea. Specifically, a list of the products that should be generated from the acquisition programs is provided. The problem is that the unexperienced companies in the defence systems industry cannot easily know how to approach the new regulation. The purpose of this study is to devise a possible remedy to solve the problem. To do so, we first review the list of the products that are required by DAPA. Then, an appropriate systems engineering processes is studied for each product. Then, a necessary link between each product and SE process activity is identified and summarized. The result obtained may be useful as a stepping stone to develop more efficient method for the list of the products.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.24-32
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM(or SRAM) cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1)simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering, like smoothing and segmentation, may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.