• 한국재료학회지
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• 제24권9호
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• pp.502-507
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• 2014

Recently, improvement in the conversion efficiency of silicon-based solar cells has been achieved by decreasing emitter doping concentration, because the lightly doped emitter can effectively prevent the recombination of electrons and holes generated by solar light irradiation. This type of emitter is very thin due to the low doping concentration, thus conductive materials (i.e., silver) used for front electrodes can easily penetrate the emitter during a firing process because of their large diffusivity in silicon. This results in junction leakage currents which might reduce cell efficiencies. In this study, $Al_2O_3$-coated Ag powders were synthesized by an ultrasonic spray pyrolysis method and applied to the conductive materials of the front electrode to control the junction leakage current. The $Al_2O_3$ shell obstructs the Ag diffusion into the emitter during the firing process. The powder is spherical with a core-shell structure and the thickness of the $Al_2O_3$ shell is tens of nanometers. Solar cells were fabricated using pure Ag powders or the $Al_2O_3$-coated Ag powder as front electrode materials, and the conversion efficiency and junction leakage current were compared to investigate the role of the $Al_2O_3$ shell during the firing processes.

• 한국진공학회지
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• 제12권4호
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• pp.239-250
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• 2003

실리콘-게르마늄 이종접합 바이폴라 트랜지스터 (SiGe HBT)에서 발생하는 신뢰성 열화 현상을 고찰하였다. SiGe HBT의 경우에 전류이득 감소, AC특성 저하, 오프셋 전압이 자주 관찰되는데 그 원인으로는 각각 에미터-베이스 역 바이어스 전압 스트레스, 과도촉진확산 (transient enhanced diffusion), 공정 변동 (fluctuation)에 따른 베이스-콜렉터 접합 특성 저하를 들 수 있다. 에미터-베이스 접합에 역 바이어스 전압 스트레스가 걸리면 에미터-베이스 접합면의 테두리 부분에서 높은 에너지를 가지는 전자와 정공들이 생성되고, 이들 전자와 정공들이 실리콘-산화막 계면 및 산화막 내부에 전하를 띈 트랩을 생성하기 때문에 재결합에 의한 베이스 누설전류가 증가하여 소자의 전류이득은 크게 감소하게 된다. 에미터-베이스 접합과 외부 베이스의 거리가 임계 값보다 짧을 때에는 소자의 차단주파수($f_t$)가 감소하게 되는데 이것은 외부 베이스 이온주입에 의하여 내부 베이스 내의 도펀트의 확산이 촉진되어 나타나는 현상이다. 외부 베이스 이온주입 에너지가 충분하지 않은 경우에는 콜렉터-베이스 접합의 턴온 전압이 감소하여 전류-전압 특성 곡선에서 오프셋 전압이 발생하게 된다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권7호
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• pp.521-524
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• 1999

Nb silicide was formed on the Si micro-tip arrays in order to improve field emission properties of Si-tip field emitter array. After silicidization of the tips, the etch-back process, by which gate insulator, gate electrode and photoresist were deposited sequentially and gate holes were defined by removing gradually the photoresist by $O_2$ plasma from the surface, was applied. Si nitride film was used as a protective layer in order to prevent oxygen from diffusion into Nb silicide layer and it was identified that the NbSi2 was formed through annealing in $N_2$ ambient at $1100^{\circ}C$ for 1 hour. By the Nb silicide coating on Si tips, the turn-on voltage was decreased from 52.1 V to 32.3 V and average current fluctuation for 1 hour was also reduced from 5% to 2%. Also, the fabricated Nb silicide-coated Si tip FEA emitted electrons toward the phosphor and light emission was obtained at the gate voltage of 40~50 V.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.68-69
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• 2007

To make cost-effective solar cells, We have to use low cost material or make short process time or high temperature process. In solar cells, formation of emitter is basic and important technique according to build-up P-N junction. Diffusion process using spin-on dopants has all of this advantage. In this paper, We investigated n+ emitter formation spin-on dopants to apply crystalline silicon solar cells. We known variation of sheet resistance according to variation of temperature and single-crystalline and multi-crystalline silicon wafer using Honeywell P-8545 phosphorus spin-on dopants. We obtain uniformity of sheet resistance within 3~5% changing RPM of spin coater.

• 대한전자공학회논문지
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• 제23권1호
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• pp.42-45
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• 1986

This paper introduces novel functionally integrated logic elements which are conceptuallized for large scale integrated circuits. Efforts are made to minimize the gate size as well as to reduce the operational voltage, without sacrificing the speed performance of the gates. The process used was a rather conventional collector diffusion isolation(CDI) process. New gate structures are formed by merging several transistors of a gate in the silicon substrate. Thested elements are CML(Current Mode Logic) and EECL (Emitter-to-Emitter Coupled Logic)gates. The obtained experimental results are power-delay product of 6~11pJ and delay time/gate of 1.6~1.8 ns, confirming the possibility of these novel gate structures as a VLSI-candidate.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.81.1-81.1
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• 2015

최근 실리콘(Si) 원재료 가격의 하락으로 인하여, 태양광 시장에서 성능 좋은 저가의 태양광 모듈을 요구하고 있다. 즉, 와트(W)당 낮은 가격의 태양광 모듈을 선호하기 때문에 경쟁력을 갖추기 위하여서는 많은 출력을 낼 수 있는 고효율의 태양전지가 요구된다. 그래서 주목을 받고 있는 것이 N-type 실리콘 기판을 사용한 고효율 태양전지이다. 하지만, n-type Si 기판의 경우, pn 접합의 형성을 위하여서 기존의 열 확산(Thermal diffusion)법에 의한 에미터(Emitter) 형성방법은 양질의 pn접합을 형성하기에는 한계가 있다. 그로 인하여 주목하고 있는 기술이 반도체 공정에서 널리 사용되고 있는 이온 주입(Ion implantation)방식이다. 이 기술은 양질의 에미터 형성을 위하여, 동일한 양의 불순물(dopant) 주입, 정확한 접합 깊이 제어 등이 가능한 방법으로 고효율 태양전지 제작에 필수적이며, 가능한 기술이라고 할 수 있다. 본 발표에서는 어플라이드 머트리얼즈(Applied Materials)사가 보유하고 있는 고효율 태양전지 제작에 필수적인 이온주입방식의 기술과 양산화 가능한 관련장비 등을 소개 하고자 한다.

• E2M - 전기 전자와 첨단 소재
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• 제10권10호
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• pp.1034-1040
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• 1997

A solar cell conversion effiency was degraded by grain boundary effect in polycrystalline silicon. Grain boundaries acted as potential barriers as well as recombination centers for the photo-generated carriers. To reduce these effects of the grain boundaries we investigated various influencing factors such as emitter thickness thermal treatment preferential chemical etching of grain boundaries grid design contact metal and top metallization along boundaries. Pretreatment in $N_2$atmosphere and gettering by POCl$_3$and Al were performed to obtain multicrystalline silicon of the reduced defect density. Structural electrical and optical properties of slar cells were characterized before and after each fabrication process. Improved conversion efficiencies of solar cell were obtained by a combination of pretreatment above 90$0^{\circ}C$ emitter layer of 0.43${\mu}{\textrm}{m}$ Al diffusion in to grain boundaries on rear side fine grid finger top Yb metal and buried contact metallization along grain boundaries.

• 반도체디스플레이기술학회지
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• 제16권1호
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• pp.65-69
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• 2017

This paper presents a Technology-CAD (TCAD) simulation of the characteristics of crystalline Si pillar array solar cells. The junction depth and the surface concentration of the solar cells were optimized to obtain the targeted sheet resistance of the emitter region. The diffusion model was determined by calibrating the emitter doping profile of the microscale silicon pillars. The dimension parameters determining the pillar shape, such as width, height, and spacing were varied within a simulation window from ${\sim}2{\mu}m$ to $5{\mu}m$. The simulation showed that increasing pillar width (or diameter) and spacing resulted in the decrease of current density due to surface area loss, light trapping loss, and high reflectance. Although increasing pillar height might improve the chances of light trapping, the recombination loss due to the increase in the carrier's transfer length canceled out the positive effect to the photo-generation component of the current. The silicon pillars were experimentally formed by photoresist patterning and electroless etching. The laboratory results of a fabricated Si pillar solar cell showed the efficiency and the fill factor to be close to the simulation results.

• 대한전자공학회논문지
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• 제18권1호
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• pp.7-19
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• 1981

실리콘 양극산화방법으로 실리콘에서의 불순물 분포를 측정하였다. 전해액으로 Ethylene Glycol-KNO3(0.04N)을 사용하였고, 200V의 전압을 가했을 때 한번의 양극산화에 의하여 삭감되는 실리콘 두께는 웨이퍼 타이프에 관계없이 460±40A이다. Predeposition후의 보론과 아세닉의 분포를 구하였고 이 분포에 의하여 불순물 농도에 따른 확산계수를 계산하였다. 또한 npn트란지스터 구조에서 아세닉 에미터와 브론 베이스간의 상호작용에 의한 베이스 pull-in 현상을 관찰하였다.

• 대한전자공학회논문지
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• 제23권6호
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• pp.929-935
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• 1986

In this paper, we describe the physical modelling and numerical aspects of a program called PRECISE(Program for Efficient Calculation of Impurity Profile in Semiconductor by Elimination) which calcualtes a two-dimensional impurity profile in silicon due to diffusion and ion implantation steps. The PRECISE enables rapid prediction of the two-dimensional impurity profile near the mask edge-or the bird's beak during the local oxidation process. This has been developed by modifying the existing one-dimentional simulator, DIFSIM(DIFfusion SIMulator to include models for arsenic diffusion and emitter dip effect which were found out to agree fairly well with the xperimental data.