• Title/Summary/Keyword: embedded software

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An exploratory study of stress wave communication in concrete structures

  • Ji, Qing;Ho, Michael;Zheng, Rong;Ding, Zhi;Song, Gangbing
    • Smart Structures and Systems
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    • v.15 no.1
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    • pp.135-150
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    • 2015
  • Large concrete structures are prone to cracks and damages over time from human usage, weathers, and other environmental attacks such as flood, earthquakes, and hurricanes. The health of the concrete structures should be monitored regularly to ensure safety. A reliable method of real time communications can facilitate more frequent structural health monitoring (SHM) updates from hard to reach positions, enabling crack detections of embedded concrete structures as they occur to avoid catastrophic failures. By implementing an unconventional mode of communication that utilizes guided stress waves traveling along the concrete structure itself, we may be able to free structural health monitoring from costly (re-)installation of communication wires. In stress-wave communications, piezoelectric transducers can act as actuators and sensors to send and receive modulated signals carrying concrete status information. The new generation of lead zirconate titanate (PZT) based smart aggregates cause multipath propagation in the homogeneous concrete channel, which presents both an opportunity and a challenge for multiple sensors communication. We propose a time reversal based pulse position modulation (TR-PPM) communication for stress wave communication within the concrete structure to combat multipath channel dispersion. Experimental results demonstrate successful transmission and recovery of TR-PPM using stress waves. Compared with PPM, we can achieve higher data rate and longer link distance via TR-PPM. Furthermore, TR-PPM remains effective under low signal-to-noise (SNR) ratio. This work also lays the foundation for implementing multiple-input multiple-output (MIMO) stress wave communication networks in concrete channels.

CHARMS: A Mapping Heuristic to Explore an Optimal Partitioning in HW/SW Co-Design (CHARMS: 하드웨어-소프트웨어 통합설계의 최적 분할 탐색을 위한 매핑 휴리스틱)

  • Adeluyi, Olufemi;Lee, Jeong-A
    • Journal of the Korea Society of Computer and Information
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    • v.15 no.9
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    • pp.1-8
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    • 2010
  • The key challenge in HW/SW co-design is how to choose the appropriate HW/SW partitioning from the vast array of possible options in the mapping set. In this paper we present a unique and efficient approach for addressing this problem known as Customized Heuristic Algorithm for Reducing Mapping Sets(CHARMS). CHARMS uses sensitivity to individual task computational complexity as well the computed weighted values of system performance influencing metrics to streamline the mapping sets and extract the most optimal cases. Using H.263 encoder, we show that CHARMS sieves out 95.17% of the sub-optimal mapping sets, leaving the designer with 4.83% of the best cases to select from for run-time implementation.

Smart grid and nuclear power plant security by integrating cryptographic hardware chip

  • Kumar, Niraj;Mishra, Vishnu Mohan;Kumar, Adesh
    • Nuclear Engineering and Technology
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    • v.53 no.10
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    • pp.3327-3334
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    • 2021
  • Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.

Design and Evaluation of the Internet-Of-Small-Things Prototype Powered by a Solar Panel Integrated with a Supercapacitor

  • Park, Sangsoo
    • Journal of the Korea Society of Computer and Information
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    • v.26 no.11
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    • pp.11-19
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    • 2021
  • In this paper, we propose a prototype platform combined with the power management system using, as an auxiliary power storage device, a supercapacitor that can be fast charged and discharged with high power efficiency as well as semi-permanent charge and discharge cycle life. For the proposed platform, we designed a technique which is capable of detecting the state of power cutoff or resumption of power supplied from the solar panel in accordance with physical environment changes through an interrupt attached to the micro-controller was developed. To prevent data loss in a computing environment in which continuous power supply is not guaranteed, we implemented a low-level system software in the micro-controller to transfer program context and data in volatile memory to nonvolatile memory when power supply is cut off. Experimental results shows that supercapacitors effectively supply temporary power as auxiliary power storage devices. Various benchmarks also confirm that power state detection and transfer of program context and data from volatile memory to nonvolatile memory have low overhead.

Method of In-Vehicle Gateway to Reduce the Reprogramming Time (리프로그래밍 시간 단축을 위한 차량 게이트웨이 개선 방안)

  • Kim, Jin-Ho;Ha, Kyung-Jae
    • Journal of Convergence for Information Technology
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    • v.9 no.7
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    • pp.25-32
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    • 2019
  • This paper proposes the method of an in-vehicle gateway to reduce the reprogramming time for the ECU (Electronic Control Unit). In order to reduce the reprogramming time, the gateway must prohibit transmitting messages, that are not related to reprogramming, to the destination CAN network, and no ECU should diagnose the DTC(Diagnostic Trouble Code) that indicates CAN communication error caused by prohibiting CAN messages by the gateway. Moreover, STmin, which are the minimum time between two consecutive CAN messages, should be minimized. In order to do this, this paper proposes the method that uses the link control command specified in UDS(Unified Diagnostic Services) and hardware based gateway functionality that are supported by the latest MCU(Micro Controller Unit). The proposed method is developed using TC275 based embedded system, and its results are presented.

A Cortex-M0 based Security System-on-Chip Embedded with Block Ciphers and Hash Function IP (블록암호와 해시 함수 IP가 내장된 Cortex-M0 기반의 보안 시스템 온 칩)

  • Choe, Jun-Yeong;Choi, Jun-Baek;Shin, Kyung-Wook
    • Journal of IKEEE
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    • v.23 no.2
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    • pp.388-394
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    • 2019
  • This paper describes a design of security system-on-chip (SoC) that integrates a Cortex-M0 CPU with an AAW (ARIA-AES- Whirlpool) crypto-core which implements two block cipher algorithms of ARIA and AES and a hash function Whirlpool into an unified hardware architecture. The AAW crypto-core was implemented in a small area through hardware sharing based on algorithmic characteristics of ARIA, AES and Whirlpool, and it supports key sizes of 128-bit and 256-bit. The designed security SoC was implemented on FPGA device and verified by hardware-software co-operation. The AAW crypto-core occupied 5,911 slices, and the AHB_Slave including the AAW crypto-core was implemented with 6,366 slices. The maximum clock frequency of the AHB_Slave was estimated at 36 MHz, the estimated throughputs of the ARIA-128 and the AES-128 was 83 Mbps and 78 Mbps respectively, and the throughput of the Whirlpool hash function of 512-bit block was 156 Mbps.

Development of High Precision Impedance Measurement Systems in Specific Ranges Using a Microprocessor (마이크로프로세서를 이용한 특정 영역에서 고정밀 임피던스 측정 시스템 개발)

  • Ryu, Jae-Chun;Lee, Myung-Eui
    • Journal of Advanced Navigation Technology
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    • v.23 no.4
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    • pp.316-321
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    • 2019
  • In this paper, by applying the constant current principle we develop an impedance measurement system which can measure the high precision impedance of various electric materials by using microprocessor. This measurement system board has an interface device for acquiring digital data from an external device including an impedance measuring device, and system software is also developed by a firmware program executed on such an embedded board. It can measure the high precision impedance of a specific band with 1/32768 precision by using 15-bit ADC(analog to digital converter) and calculate it to the five digits to the right of the decimal point(fraction part). Data is transmitted through a USB interface of a general computer and a measuring device to manage digital data. An impedance measurement system equipped with a communication function capable of a more general and easy-to-use interface than other equipment is developed and verified.

The efficient implementation of the multi-channel active noise controller using a low-cost microcontroller unit (저가 microcontoller unit을 이용한 효율적인 다채널 능동 소음 제어기 구현)

  • Chung, Ik Joo
    • The Journal of the Acoustical Society of Korea
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    • v.38 no.1
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    • pp.9-22
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    • 2019
  • In this paper, we propose a method that can be applied to the efficient implementation of multi-channel active noise controller. Since the normalized MFxLMS (Modified Filtered-x Least Mean Square) algorithm for the multi-channel active noise control requires a large amount of computation, the difficulty has lied in implementing the algorithm using a low-cost MCU (Microcontoller Unit). We implement the multi-channel active noise controller efficiently by optimizing the software based on the features of the MCU. By maximizing the usage of single-cycle MAC (Multiply- Accumulate) operations and minimizing move operations of the delay memory, we can achieve more than 3 times the performance in the aspect of computational optimization, and by parellel processing using the auxillary processor included in the MCU, we can also obtain more than 4 times the performance. In addition, the usage of additional parts can be minimized by maximizing the usage of the peripherals embedded in the MCU.

Secure and Energy-Efficient MPEG Encoding using Multicore Platforms (멀티코어를 이용한 안전하고 에너지 효율적인 MPEG 인코딩)

  • Lee, Sung-Ju;Lee, Eun-Ji;Hong, Seung-Woo;Choi, Han-Na;Chung, Yong-Wha
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.20 no.3
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    • pp.113-120
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    • 2010
  • Content security and privacy protection are important issues in emerging network-based video surveillance applications. Especially, satisfying both real-time constraint and energy efficiency with embedded system-based video sensors is challenging since the battery-operated sensors need to compress and protect video content in real-time. In this paper, we propose a multicore-based solution to compress and protect video surveillance data, and evaluate the effectiveness of the solution in terms of both real-time constraint and energy efficiency. Based on the experimental results with MPEG2/AES software, we confirm that the multicore-based solution can improve the energy efficiency of a singlecore-based solution by a factor of 30 under the real-time constraint.

Proposal of a framework for evaluating the operational impact of cyber attacks on aviation weapons systems(EOICA) (항공무기체계 사이버공격에 대한 작전영향성평가 프레임워크 제안)

  • Hong, Byoung-jin;Kim, Wan-ju;Lee, Soo-jin;Lim, Jae-sung
    • Convergence Security Journal
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    • v.20 no.4
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    • pp.35-45
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    • 2020
  • Cyber attacks on the aviation weapon system, a state-of-the-art asset, have become a reality and are approaching as a constant threat. However, due to the characteristics of embedded software of the current aviation weapon system, it is managed and operated without connection to the network in peacetime, so the response management to cyber attacks is relatively weak. Therefore, when a cyber attack becomes a reality, it is urgent to prepare and evaluate measures for the adverse effects that such attack will have on the execution of the Air Tasking Order(ATO). In this paper, we propose a framework for operational impact assessment in order to avoid confusion in ATO execution and systematic response to cyber attacks on aviation weapons systems. The proposed framework is designed to minimize the negative impact on operations against cyber attacks that may occur under no warning by analyzing the impact on air operations for each aviation weapon system and standardizing countermeasures for this. In addition, it supports the operational commander to make a quick decision to command for the execution of the operation even in a situation where a cyber attack occurs.