• THE INTERNATIONAL COMMERCE & LAW REVIEW
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• v.60
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• pp.47-77
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• 2013

The way for seller to procure the goods for selling is to produce the goods at his own factory and to buy the manufactured goods from the other company. In order to produce the goods for selling the seller have to obtain the resource from the domestic company or overseas. In the middle of producing the goods to sell, seller may breach the right of a third party based on intellectual property rights. That is to say, seller may use the machine that has not itself been patented and use a process which has been patented by a third party. Seller may manufacture the goods which themselves are subject to the third party industrial property rights. Nowadays it is stressed the importance of intellectual property rights such as a patent, brand, and design. These factors consist of the core elements of the competitiveness of the goods. Many embedded software have been used in the various sector. So the disputes regarding to the intellectual property rights is gradually increasing in number. Article 42 of CISG defines the seller's delivery obligations and liabilities in respect to third party intellectual property rights and claims. It contains a special rule for this similar kind of defective in title, which tries to provide an proper solution to the complex problems caused by such rights and claims in international transactions. When seller will apply this clause to the business fields, there are several points to which seller should give attention. First, Intellectual property is general terms in intangible property rights, encompassing both copyright and industrial property. Which matter fall within the scope of intellectual property? The scope of intellectual property can be inferred from the relevant international conventions, which are based on broad international consensus. Second, Article 42 of CISG governs the relationship between the seller and the buyer, that is to say, questions of who has to bear the risk of third party intellectual property rights. The existence of such intellectual property rights, the remedies available and the question of acquiring goods free of an encumbrances in good faith are outside the scope of the CISG. The governing law regarding to the abovementioned matters is needed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.97-102
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• 2014

Abdelzaher et al. proposed an algorithm to determine the schedulability of aperiodic tasks on multiprocessor systems, and proved that the aperiodic tasks are schedulable if the upperbound of synthetic utilization is less than or equal to 0.59. But this algorithm has a drawback in that if some tasks, even though they are completed and have no more execution times, are included in the current invocation set, their execution times and deadlines are added to the synthetic utilization. This may lead to a problem in which actually schedulable tasks are decided not to be schedulable. In this paper, we recognize the above mentioned problem and propose an improved synthetic utilization method that can be used to schedule aperiodic tasks more efficiently on multiprocessor systems.

• KIPS Transactions on Software and Data Engineering
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• v.2 no.12
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• pp.829-840
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• 2013

This paper proposes a modified RRT (Rapidly exploring Random Tree) algorithm utilizing a heuristic input analysis and suggests a test case generation method from Simulink/Stateflow model using the proposed RRT algorithm. Though the typical RRT algorithm is an efficient method to solve the reachability problem to definitely be resolved for generating test cases of model in a black box manner, it has a drawback, an inefficiency of test case generation that comes from generating random inputs without considering the internal states and the test targets of model. The proposed test case generation method increases efficiency of test case generation by analyzing the test targets to be satisfied at the current state and heuristically deciding the inputs of model based on the analysis during expanding an RRT, while maintaining the merit of RRT algorithm. The proposed method is evaluated with the models of ECUs embedded in a commercial passenger's car. The performance is compared with that of the typical RRT algorithm.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1235-1238
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• 2004

Thresholding has been used to reduce the number of gray values in images. Typically, a single threshold value has been used, resulting in two gray level images. Image reduction of one single threshold value, however, may lose too much of the high-frequency edge information. Thus, dynamic thresholding that uses a different threshold for each pixel is preferred instead of using a single threshold value. Dynamic thresholding can preserve high frequency details as well as reduce the size of images. Since it takes long time to perform existing software dynamic thresholding in an embedded system, this paper proposes and implements a circuit by using a FPGA in order to perform a real-time dynamic thresholding,. The proposed circuit consists of two counters, and threshold look-up table, and control unit. The values of two counters determine each pixel position, the threshold look-up table converts each pixel value into other value, and the control unit generates necessary control signals. On arriving from a camera to the proposed circuit, each pixel is compared with its threshold value and is converted into other gray value. An image processing system by using the proposed circuit will be implemented and some experiments will be performed.

• KIPS Transactions on Computer and Communication Systems
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• v.9 no.10
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• pp.213-220
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• 2020

The power consumption and performance of hardware-based mobile and IoT embedded systems that require high specifications are one of the important issues of these systems. In particular, the problem of excessive power consumption is because it causes a problem of increasing heat generation and shortening the life of the device. In addition, in the same environment, software also needs to perform stable operation in limited power and memory, thereby increasing power consumption of the device. In order to solve these issues, we propose a Low level power improvement via identifying performance dissipation. The proposed method identifies complex modules (especially Cyclomatic complexity, Coupling & Cohesion) through code visualization, and helps to simplify low power code patterning and performance code. Therefore, through this method, it is possible to optimize the quality of the code by reducing power consumption and improving performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.76-84
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• 2009

This paper proposes a SOC platform which is eligible for education and application SOC design. The platform, fully synthesizable and reconfigurable, includes the OpenRISC embedded processor, some basic peripherals such as GPIO, UART, debug interlace, VGA controller and WISHBONE interconnect. The platform uses a set of development environment such as compiler, assembler, debugger and RTOS that is built for HW/SW system debugging and software development. Designed SOC, IPs and Testbenches are described in the Verilog HDL and verified using commercial logic simulator, GNU SW development tool kits and the FPGA. Finally, a multimedia SOC derived from the SOC platform is implemented to ASIC using the Magnachip cell library based on 0.18um 1-poly 6-metal technology.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.3
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• pp.111-117
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• 2018

Heterogeneous multi-core environment integrated with different functional cores is the powerful tool for the embedded system that became more complex and diverse. Specialized application requires one chip solution with different operating system over different cores. But this heterogeneity causes difficult configuration of the development environment, makes hard to develop and test software. We show the environment of heterogeneous multi-core processing can be mapped to symmetric multi-core environment. We construct Linux based RPMsg for the data exchange between processes similar with the heterogeneous multi-core RPMsg and experiment that the proposed environment can be used to reduce the steps of the heterogeneous multi-core application development. With this simplification, we suggest simulation method for easy development and debugging the heterogeneous multicore environment that makes complex steps to simple.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.6
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• pp.3230-3253
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• 2017

Android malware steals users' private information, and embedded unsafe advertisement (ad) libraries, which execute unsafe code causing damage to users. The majority of such traffic is HTTP and is mixed with other normal traffic, which makes the detection of malware and unsafe ad libraries a challenging problem. To address this problem, this work describes a novel HTTP traffic flow mining approach to detect and categorize Android malware and unsafe ad library. This work designed AndroCollector, which can automatically execute the Android application (app) and collect the network traffic traces. From these traces, this work extracts HTTP traffic features along three important dimensions: quantitative, timing, and semantic and use these features for characterizing malware and unsafe ad libraries. Based on these HTTP traffic features, this work describes a supervised classification scheme for detecting malware and unsafe ad libraries. In addition, to help network operators, this work describes a fine-grained categorization method by generating fingerprints from HTTP request methods for each malware family and unsafe ad libraries. This work evaluated the scheme using HTTP traffic traces collected from 10778 Android apps. The experimental results show that the scheme can detect malware with 97% accuracy and unsafe ad libraries with 95% accuracy when tested on the popular third-party Android markets.

• Journal of the Korea Institute of Military Science and Technology
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• v.20 no.5
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• pp.688-699
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• 2017

Model-based test, a well-known method of the black box tests, is consisted of the following four steps : model construction using requirement, test case generation from the model, execution of a SUT (software under test) and detection failures. Among models constructed in the first step, state-based models such as UML standard State Machine are commonly used to design event-based embedded systems (e.g., weapon control systems). To generate test cases from state-based models in the next step, coverage-based techniques such as state coverage and transition coverage are used. Round-trip path coverage technique using W-Method, one of coverage-based techniques, is known as more effective method than others. However it has a limitation of low failure observability because the W-Method technique terminates a testing process when arrivals meet states already visited and it is hard to decide the current state is completely same or not with the previous in the case like the GUI environment. In other words, there can exist unrevealed faults. Therefore, this study suggests a Extended W-Method. The Extended W-Method extends the round-trip path to a final state to improve failure observability. In this paper, we compare effectiveness and efficiency with requirement-item-based technique, W-Method and our Extended W-Method. The result shows that our technique can detect five and two more faults respectively and has the performance of 28 % and 42 % higher failure detection probability than the requirement-item-based and W-Method techniques, respectively.

• Journal of the Korea Convergence Society
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• v.6 no.1
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• pp.23-28
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• 2015

Teaching programming skills is not only required for computer related departments but through the area of engineering and natural science. Moreover recently teaching programming skill is emphasized in software education for primary schools and secondary schools. Since programming ability is considered an essencial element of national competitiveness, we need programming learning system which alleviates the difficulty. We implemented Blockly webc Programming Convergent Learning System which is based on the graphic tools called Blockly by Google. Inside system problem sets for the programming beginners are embedded in the system. These problem sets are gone under more than 20 years verification and these problem sets may be used to help beginning programmers escape novice coder in short time. Blockly webc Programming Convergent Learning System together with already developed Simple Visual Language2 Programming Learning System is expected to play an important role as a programming learning system for the beginners.