• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.4
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• pp.231-241
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• 2011

Recently, system virtualization has been applied to consumer electronics (CE) such as smart mobile phones. Although multi-core processors have become a viable solution for complex applications of consumer electronics, the issue of utilizing multi-core resources in the virtualization layer has not been researched sufficiently. In this paper, we present a new hypervisor design and implementation for multi-core CE devices. We concretely describe virtualization methods for a multi-core processor and multi-core-related subsystems. We also analyze bottlenecks of network performance in a virtualization environment that supports multimedia applications and propose an efficient virtual interrupt distributor. Our new multi-core hypervisor improves network performance by 5.5 times as compared to a hypervisor without the virtual interrupt distributor.

• Journal of the Korea Society of Computer and Information
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• v.15 no.3
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• pp.1-10
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• 2010

As processor platforms are continuously moving toward wireless mobile systems, embedded mobile processors are expected to perform more and more powerful, and therefore the development of an efficient power management algorithm for these battery-operated mobile and handheld systems has become a critical challenge. It is well known that a memory system is a main performance limiter in the processor point of view. Although many DVFS studies have been considered for the efficient utilization of limited battery resources, recent works do not explicitly show the interaction between the processor and the memory. In this research, to properly reflect short/long-term memory access patterns of the embedded workloads in wireless mobile processors, we propose a memory buffer utilization as a new index of DVFS level prediction. The simulation results show that our solution provides 5.86% energy saving compared to the existing DVFS policy in case of memory intensive applications, and it provides 3.60% energy saving on average.

• The Journal of the Korea institute of electronic communication sciences
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• v.19 no.2
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• pp.417-426
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• 2024

In general, the implementation of machine learning requires prior knowledge and experience with deep learning models, and substantial computational resources and time are necessary for data processing. As a result, machine learning encounters several limitations when deployed on embedded processors. To address these challenges, this paper introduces a novel approach where a genetic algorithm is applied to the convolution operation within the machine learning process, specifically for performing a selective convolution operation.In the selective convolution operation, the convolution is executed exclusively on pixels identified by a genetic algorithm. This method selects and computes pixels based on a ratio determined by the genetic algorithm, effectively reducing the computational workload by the specified ratio. The paper thoroughly explores the integration of genetic algorithms into machine learning computations, monitoring the fitness of each generation to ascertain if it reaches the target value. This approach is then compared with the computational requirements of existing methods.The learning process involves iteratively training generations to ensure that the fitness adequately converges.

• IEMEK Journal of Embedded Systems and Applications
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• v.3 no.3
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• pp.158-166
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• 2008

These days, mobile embedded systems adopt flash memory capable of XIP feature since they can reduce memory usage, power consumption, and software load time. XIP provides direct access to ROM and flash memory for processors. However, using XIP incurs unnecessary degradation of applications' performance because direct access to ROM and flash memory shows more delay than that to main memory. In this paper, we propose a memory management framework, dynamic XIP, which can resolve the performance degradation of using XIP. Using a constrained RAM cache, dynamic XIP can dynamically change XIP region according to page access pattern to reduce performance degradation in execution time or energy consumption resulting from native XIP problem. The proposed framework consists of a page profiler gathering applications' memory access pattern using PMU and an XIP manager deciding that a page is accessed whether in main memory or in flash memory. The proposed framework is implemented and evaluated in Linux kernel. Our evaluation shows that our framework can reduce execution time at most 25% and energy consumption at most 22% compared with using XIP-only case adopted in general mobile embedded systems. Moreover, the evaluation shows that in execution time and energy consumption, our modified LRU algorithm with code page filters can reduce more than at most 90% and 80% respectively compared with applying just existing LRU algorithm to dynamic XIP.

• Proceedings of the IEEK Conference
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• 2000.06c
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• pp.67-70
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• 2000

In a distributed real-time system(DRTS), testing and debugging are difficult and critical procedures since they implies several problems like probe effects, nondeterminism, and complex communication patterns. In this paper, we describe the design and implementation of a real-time monitor for ARM processors which are frequently used for embedded applications. The focus of design is to help users debug real-time programs while minimizing the probe effect. Our monitor provides cross debugging features like down-loading from host, break-point based debugging features, and watch-point debugging features for real-time applications. We developed the debugger for ARM processor and debugger has been used for kernel program.

• Journal of Ocean Engineering and Technology
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• v.8 no.1
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• pp.50-61
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• 1994

A 300 meter class ROV(CROV300) is composed of three parts : a surface unit, a tether cable and an underwater vehicle. The vehicle controller is based on two processors : an Intel 8097-16-bit one chip micro-processor and a Texas Instruments TMS320E25 digital signal processor. In this paper, the surface controller, the vehicle controller and peripheral devices interfaced with the processors are described. These controllers transmit/receive measured status data and control commands through RS422 serial communication. Depth, heading, trimming, camera tilting, and leakage signals are acquired through the embedded AD converters of the 8097. On the other hand, altitude of ROV and lbstacle avoidance signals are processed by the DSP processor and periodically fetched by the 8097. The processor is interfaced with a 4-channel 12-bit D/A converter to generate control signals for DC motors an dseveral transistors to handle the relays for on/off switching of external devices.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.252-259
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• 2007

With the rapid development of multimedia applications and wireless communication networks, consumer demand for video-over-wireless capability on mobile computing systems is growing rapidly. In this regard, this paper introduces YUV-aware instructions that enhance the performance and efficiency in the processing of color image and video. Traditional multimedia extensions (e.g., MMX, SSE, VIS, and AltiVec) depend solely on generic subword parallelism whereas the proposed YUV-aware instructions support parallel operations on two-packed 16-bit YUV (6-bit Y, 5-bits U, V) values in a 32-bit datapath architecture, providing greater concurrency and efficiency for color image and video processing. Moreover, the ability to reduce data format size reduces system cost. Experiment results on a representative dynamically scheduled embedded superscalar processor show that YUV-aware instructions achieve an average speedup of 3.9x over the baseline superscalar performance. This is in contrast to MMX (a representative Intel#s multimedia extension), which achieves a speedup of only 2.1x over the same baseline superscalar processor. In addition, YUV-aware instructions outperform MMX instructions in energy reduction (75.8% reduction with YUV-aware instructions, but only 54.8% reduction with MMX instructions over the baseline).

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.4
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• pp.169-175
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• 2018

Recently, power dissipation issue is very significant not only in high-end modern processors but also in embedded systems and mobile devices. Based on the power dissipation, hardware and software designers can correctly find the power/performance tradeoffs. Most power analysis tools calculate power dissipation when chip layout or floor planning are finished. In this paper, a trace-driven simulator that can interact with power analysis tool for an embedded microprocessor has been developed. Using MiBench embedded benchmarks as input, the trace-driven simulation has been performed to estimate the average power dissipation which is faster than the conventional tools.

• Journal of Broadcast Engineering
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• v.24 no.6
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• pp.1064-1071
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• 2019

Multiview stereo matching algorithm is used to reconstruct 3D shape from a set of 2D images. Conventional multiview stereo algorithms have been implemented on high-performance hardware due to the heavy complexity that contains a large number of calculations in each step. However, as the performance of mobile graphics processors has recently increased rapidly, complex computer vision algorithms can now be implemented on mobile devices like a smartphone and an embedded board. In this paper we parallelize an multiview stereo algorithm using OpenCL on mobile GPU and provide various optimization techniques on the embedded hardware with limited resource.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.05a
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• pp.600-602
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• 2021

With the development of the mobile industry and growing interest in artificial intelligence (AI) technology, a lot of research for AI processors which applicable to embedded systems is under study. When implementing AI to embedded systems, the design should be considered the restriction of resource and power consumption. Moreover, it is efficient to include a dedicated hardware accelerator in order to complement the low computational performance of the embedded system. In this paper, we propose an stand-alone embedded AI processor. The proposed AI processor includes a hardware accelerator that is dedicated to the distance-based AI algorithm and a general-purpose MCU that supports flexible programmability for application to various embedded systems. The AI processor was designed with Verilog HDL and verified by implementing on Field Programmable Gate Array (FPGA).