• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.5
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• pp.191-196
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• 2016

Recently, power dissipation is a very significant issue not only in embedded systems and mobile devices but also in high-end modern processors. Especially, by the prevalent use of smart phones and tablet PCs, low power consumption of microprocessors is requisite. In this paper, a fast power measurement tool for a high performance microprocessor based on the trace-driven simulator has been developed. The power model of the microprocessor consists of complex combinational circuits, array structures, and CAM structures. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed to estimate the average power dissipation of each program.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.1
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• pp.219-224
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• 2017

Recently, the importance of DRAM is very significant not only in embedded systems and mobile devices but also in high-end modern microprocessors and multicore processors. To keep up with this, both industry and academia have actively studied various types of future DRAMs. Therefore, accurate DRAM model is requisite when evaluating the microprocessor performance. In this paper, a microprocessor trace-driven simulator which can couple with the cycle-accurate DRAM simulator has been developed. Using SPEC 2000 benchmarks as input, the effect of cycle-accurate DDR3 model on the microprocessor performance has been evaluated.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.3
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• pp.323-332
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• 2014

Stepper motor is widely used in positioning applications due to its durability and high torque to inertia ratio as well as low cost and ability to be easily controlled with open-loop. Due to increased resolution of position control and improved stability of motion control, microstepping has drawn attention in industry since it was introduced in 1970s. With the increase in computational power and decrease in cost of embedded processors in recent years, drives and control systems for stepper motors have become more sophisticate than ever. Thus, closed-loop control methods have been developed to improve the performance of the stepper motors. In this paper, we review not only basic principles of conventional control methods used for stepper motors but also that of microstepping control. In addition, we surveyed recent development in nonlinear control methods applied to stepper motors. The nonlinear control methods are presented in the view of Lyapunov stability. Nonlinear torque disturbance observer, sliding mode control, and nonlinear phase compensation are also presented.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11B
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• pp.1659-1666
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• 2010

The High maneuver missiles use various interfaces and high speed guidance and control loop. Hardware-in-the-Loop(HWIL) simulation control system, therefore, should have high performance computing power and hardware interface capabilities, and should be developed using IT technology with which real time operating system, embedded system, data communication technology, and real time hardware control are integrated. This paper suggests the control system design techniques, such as a system hardware configuration, a job distribution algorithm for high performance multi-processors, a real time calculation and control mechanism, inter-processor communication mechanism, and a real time data acquisition technique, to perform the HWIL simulation for high maneuver missile system.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.34 no.6
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• pp.230-237
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• 1985

Shortest path calculations for a large-scale network have to be performed using a decomposition techniqre, since the calculations require large memory size which increases by the square of the number of vertices in the network. Also, the calculation time increases by the cube of the number of vertices in the network. In the decomposition technique,the network is broken into a number of smaller size subnetworks for each of which shortest paths are computed. A union of the solutions provides the solution of the original network. In all of the decomposition algirithms developed up to now, boundary vertices which divide all the subnetworks have to be included in computing shortest paths for each subnetwork. In this paper, an improved algorithm is developed to reduce the number of boundary vertices to be engaged. In the algorithm, only those boundary vertices that are directly connected to the subnetwork are engaged. The algorithm is suitable for an application to real time computation using a parallel processor system which consists of a number of micro-computers or prcessors. The algorithm has been applied to a 39- vertex network and a 232-vertex network. The results show that it is efficient and has better performance than any other algorithms. A parallel processor system has been built employing an MZ-80 micro-computer and two Z-80 microprocessor kits. The former is used as a master processor and the latter as slave processors. The algorithm is embedded into the system and proven effective for real-time shortest path computations.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.4
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• pp.1947-1953
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• 2011

OSEK/VDX is a joint project aiming at an industry standard for ECUs in vehicles and OSEK OS is a real-time operating system that meets OSEK/VDX specifications. In this paper, we suggest an implementation of task switching and interrupt handling mechanisms of OSEK operating system based on ARM processors. Considering the requirements of OSEK OS and characteristics of ARM processor, we have designed task switching and interrupt handling mechanisms. For evaluating the validation of the suggested mechanisms, we have checked the functional correctness on an experimental embedded board with ARM processor and calculated the time of task switching and interrupt handling.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06b
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• pp.261-266
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• 2007

내장형 시스템에 보다 강력한 성능이 요구됨에 따라 내장형 마이크로 프로세서는 보다 깊은 파이프라인을 채택하고 있다. 따라서, 내장형 마이크로 프로세서는 보다 정확한 분기 예측기를 필요로 하고 있다. 이러한 상황에서 분기 예특기의 구조, 성능 및 전력 소모와 전체 시스템의 전력 소모 사이의 trade-off를 분석하는 것은 매우 중요하다. 내장형 환경에서 시스템의 전력 소모는 설계 시 매우 중요하게 고려되어야 한다. 특히 내장형 시스템의 요구사항은 동작할 응용 프로그램에 의하여 규정되고, 전력 소모도 응용프로그램의 구조와 강하게 연관되어 있다. 본 논문의 목표는 내장형 환경에서 성능-전력 공간에서 분기 예측기를 분석하는 기법을 제시하는 것에 있다. 이를 통하여, 분기 예측기 테이블의 성능-전력을 고려한 최적화된 크기를 찾을 수 있다. 이러한 목표는 수학적 모델링을 통한 정량적 예측의 수행 및 시뮬레이션 결과와의 비교를 통한 수학적 모델링의 검증의 과정을 통하여 이루어진다. 결과는 우리의 수학적 모델이 성능-전력 공간에서 분기 예측기 테이블의 최적화된 크기 결정의 해법을 제공하고 있음을 보여주고 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.50-61
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• 2010

Nowadays, the SoC is watched by all over the world with interest. The design trend of the SoC is hardware and software co-design which includes the design of hardware structure in RTL level and the development of embedded software. Also the technology is toward deep-submicron and the observability of the SoC's internal state is not easy. Because of the above reasons, the SoC debug is very difficult and time-consuming. So we need a reliable debugger to find the bugs in the SoC and embedded software. In this paper, we developed a hardware debugger named OCD. It is based on IEEE 1140.1 JTAG standard. In order to verify the operation of OCD, it is integrated into the 32bit RISC processor - Core-A (Core-A is the unique embedded processor designed by Korea) and is tested by interconnecting with software debugger. When embedding the OCD in Core-A, there is 14.7% gate count overhead. We can modify the DCU which occupies 2% gate count in OCD to adapt with other processors as a debugger.

• The KIPS Transactions:PartA
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• v.12A no.4 s.94
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• pp.305-312
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• 2005

In this paper, we present algorithm-level techniques for energy-efficient design at the algorithm level using FPGAs. We then use these techniques to create energy-efficient designs for two signal processing kernel applications: fast Fourier transform(FFT) and matrix multiplication. We evaluate the performance, in terms of both latency and energy efficiency, of FPGAs in performing these tasks. Using a Xilinx Virtex-II as the target FPGA, we compare the performance of our designs to those from the Xilinx library as well as to conventional algorithms run on the PowerPC core embedded in the Virtex-II Pro and the Texas Instruments TMS320C6415. Our evaluations are done both through estimation based on energy and latency equations on high-level and through low-level simulation. For FFT, our designs dissipated an average of $50\%$ less energy than the design from the Xilinx library and $56\%$ less than the DSP. Our designs showed an EAT factor of 10 times improvement over the embedded processor. These results provide a concrete evidence to substantiate the idea that FPGAs can outperform DSPs and embedded processors in signal processing. Further, they show that PFGAs can achieve this performance while still dissipating less energy than the other two types of devices.

• The KIPS Transactions:PartA
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• v.16A no.6
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• pp.411-418
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• 2009

Vector quantization algorithm based on fuzzy clustering has been widely used in the field of data compression since the use of fuzzy clustering analysis in the early stages of a vector quantization process can make this process less sensitive to its initialization. However, the process of fuzzy clustering is computationally very intensive because of its complex framework for the quantitative formulation of the uncertainty involved in the training vector space. To overcome the computational burden of the process, this paper introduces an array architecture for the implementation of fuzzy vector quantization (FVQ). The arrayarchitecture, which consists of 4,096 processing elements (PEs), provides a computationally efficient solution by employing an effective vector assignment strategy during the clustering process. Experimental results indicatethat the proposed parallel implementation providessignificantly greater performance and efficiency than appropriately scaled alternative array systems. In addition, the proposed parallel implementation provides 1000x greater performance and 100x higher energy efficiency than other implementations using today's ARMand TI DSP processors in the same 130nm technology. These results demonstrate that the proposed parallel implementation shows the potential for improved performance and energy efficiency.