• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.397-403
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• 2015

This paper presents a new SOC test compression scheme in Embedded Deterministic Test (EDT) compression environment. Compressed test data is brought over the TAM from the tester to the cores in SOC and decompressed in the cores. The proposed scheme allows cores tested at the same time to share some test channels. By sharing free variables in these channels across test cubes of different cores decompressed at the same time, high encoding efficiency is achieved. Moreover, no excess control data is required in this scheme. The ability to reuse excess free variables eliminates the need for high precision in matching the number of test channels with the number of care bits for every core. Experimental results obtained for some SOC designs illustrate effectiveness of the proposed test application scheme.

• The Journal of Korea Robotics Society
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• v.7 no.4
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• pp.292-298
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• 2012

It is a real-time system that the system correctness depends not only on the correctness of the logical result of the computation but also on the result delivery time. Real-time Operating System (RTOS) is a software that manages the time of a microprocessor to ensure that the most important code runs first so that it is a good building block to design the real-time system. The real-time performance is achieved by using real-time mechanisms through data communication and synchronization of inter-task communication (ITC) between tasks. Therefore, test on the response time of real-time mechanisms is a good measure to predict the performance of real-time systems. This paper aims to analysis the response characteristics of real-time mechanisms in kernel space for real-time embedded Linux: RTAI and Xenomai. The performance evaluations of real-time mechanism depending on the changes of task periods are conducted. Test metrics are jitter of periodic tasks and response time of real-time mechanisms including semaphore, real-time FIFO, Mailbox and Message queue. The periodicity of tasks is relatively consistent for Xenomai but RTAI reveals smaller jitter as an average result. As for real-time mechanisms, semaphore and message transfer mechanism of Xenomai has a superior response to estimate deterministic real-time task execution. But real-time FIFO in RTAI shows faster response. The results are promising to estimate deterministic real-time task execution in implementing real-time systems using real-time embedded Linux.

• KIISE Transactions on Computing Practices
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• v.21 no.3
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• pp.173-182
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• 2015

Motion control systems are widely deployed in various industrial automation processes. The motion controller, which is a key element of motion control systems, has stringent real-time constraints. The controller must provide a short and deterministic control message transmission cycle, and minimize the actuation deviation among motor drives. To meet these requirements, hardware-based proprietary controllers have been prevalent. However, since it is becoming difficult for such an approach to meet increasing needs of system interoperability and scalability, nowadays, software-based universal motion controllers are regarded as their substitutes. Recently, embedded motion controller solutions are gaining attention due to low cost and relatively high performance. In this paper, we designed and implemented an embedded motion controller on an ARM-based evaluation board by using Xenomai real-time kernel and other open source software components. We also measured and analyzed the performance of our embedded controller under a realistic test-bed environment. The experimental results show that our embedded motion controller can provide relatively deterministic performance with synchronized control of three motor axis at 2 ms control cycle.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.463-469
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• 2016

This paper presents a compression-friendly low power test scheme in EDT environment. The proposed approach exploits scan slices reusing to reduce the switching activity during shifting for test scheme based on linear decompressor. To avoid the impact on encoding efficiency from resulting control data, a counter is utilized to generate control signals. Experimental results obtained for some larger ISCAS'89 and ITC'99 benchmark circuits illustrate that the proposed test application scheme can improve significantly the encoding efficiency of linear decompressor.

• Journal of Information Processing Systems
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• v.10 no.3
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• pp.412-428
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• 2014

Request oriented sensor networks have stricter requirements than conventional event-driven or periodic report models. Therefore, in this paper we propose a minimum energy data aggregation (MEDA), which meets the requirements for request oriented sensor networks by exploiting a low power real-time scheduler, on-demand time synchronization, variable response frame structure, and adaptive retransmission. In addition we introduce a test bed consisting of a number of MEDA prototypes, which support near real-time bidirectional sensor networks. The experimental results also demonstrate that the MEDA guarantees deterministic aggregation time, enables minimum energy operation, and provides a reliable data aggregation service.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.79-90
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• 2005

In this paper, we propose a new clustered reconfigurable interconnect network (CRIN) BIST to improve the embedding probabilities of random-pattern-resistant-patterns. The proposed method uses a scan-cell reordering technique based on the signal probabilities of given test cubes and specific hardware blocks that increases the embedding probabilities of care bit clustered scan chain test cubes. We have developed a simulated annealing based algorithm that maximizes the embedding probabilities of scan chain test cubes to reorder scan cells, and an iterative algorithm for synthesizing the CRIN hardware. Experimental results demonstrate that the proposed CRIN BIST technique achieves complete fault coverage with lower storage requirement and shorter testing time in comparison with the conventional methods.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.935-938
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• 1999

메모리 테스트는 Built-In Self Test(BIST)와 같이 메모리에 내장된 회로를 통하여 자체 점검하는 방법과 테스터를 통하여 생성된 패턴을 주입하는 방법이 있다. 테스트 패턴 생성방법으로는 각각의 고장모델에 대한 테스트 패턴을 deterministic하게 생성해주는 방법과 Pseudo Random Pattern Generator(PRPG)를 이용하여 생성하는 경우로 구분할 수 있다. 본 연구에서는 PRPG를 패턴 생성기로 사용하여 여러 가지 메모리의 결함을 대표한다고 볼 수 있는 Static 및 Dynamic Neighborhood Pattern Sensitive Fault(NPSF) 등 다양한 종류의 고장을 점검할 수 있도록 메모리 BIST를 구성하였다. 기존의 Linear Feedback Shift Register(LFSR)보다 본 연구에서 제안하는 Linear Hybrid Cellular Automata(LHCA)를 이용한 PRPG가 높고 안정된 고장 점검도를 나타내었다.

• The KIPS Transactions:PartD
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• v.14D no.6
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• pp.649-656
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• 2007

Today, controller area network(CAN) is a field bus that is nowadays widespread in distributed embedded systems due to its electrical robustness, low price, and deterministic access delay. However, its use safety-critical applications has been controversial due to dependability limitation, such as those arising from its bus topology. Thus it is important to analyze the performance of the network in terms of load of data bus, maximum time delay, communication contention, and others during the design phase of the controller area network. In this paper, a simulation algorithm is introduced to evaluate the communication performance of the vehicle network and apply software base fault injection techniques. This can not only reduce any erratic implementation of the vehicle network but it also improves the reliability of the system.