• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.9
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• pp.940-946
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• 2010

In this paper, we proposed the internal antenna on PCB(Planar Circuit Board) for achieving WWAN(Wireless Wide Area Network) operation in the laptop computer. The proposed antenna has a metal structure instead of printed pattern on PCB to improve the antenna characteristics for GSM850/900 bands. Compared to PCB embedded antenna without metal structure, the proposed antenna occupies similar area of $74{\times}11{\times}0.5\;mm^3$ with before and the bandwidth of the proposed one for GSM850/900 bands is increased 13 MHz than before. Further we confirmed that the proposed antenna has higher radiation gain of -4.45~-2.29 dBi for GSM850/900 bands than PCB embedded antenna without metal structure.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.6
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• pp.582-590
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• 2019

As Korea's low fertility and aging progress, Korea is facing a social change such as an increase of one generation by entering an aging society that has raised 14% of the population. An effective way to prevent a gas fire accident caused by an increase in one generation in an aging society is to install a control valve to forcibly shut off the gas after a set time. In this study, we developed a valve that can be opened and closed by rotating the valve left and right by transmitting power to the worm gear and the helical gear by using a motor by pressing the switch. It is easy to assemble and inspect by developing a dedicated valve that is easy to attach and detach. It was developed to enhance competitiveness by reducing cost by reducing the number of parts and product size. In addition, through endurance test, it was developed to be used for more than 9 years by repeating ON / OFF once every 12 seconds so that it can operate stably for 10,000 times for 34 hours. The instrument and PCB were designed using solid works and Altium Designer tools. Firmware development was developed in IAR Embedded Workbench environment.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.2
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• pp.175-181
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• 2016

In the conventional E-bike, a 42 V/10 A Li-ion battery drives a 24 V/10 A BLDC motor via a 6-switch PWM DC/AC inverter. The major problems of the conventional battery-fed motor drive systems are listed as follows. To charge the battery, an external battery charger (adapter) is required, which degrades the portability of E-bike users. In addition, given the high-frequency operation of the motor drive inverter, the switching losses are significant, which degrades the whole power efficiency. High-voltage batteries (42 V) require a complex battery management system (BMS), which degrades the reliability of the battery pack. In this paper, an embedded boost-converter battery charger for E-bikes is proposed. The variable output boost converter, which converts 16.8 V battery voltage to the required variable voltage of the inverter input, can use a low-voltage battery and thus improve the reliability of batteries. By varying the inverter input voltage via boost converter, a DC link voltage control method can be applied to reduce the switching frequency of the inverter, which improves the whole power efficiency. Given that the function of a flyback charger is integrated in the proposed boost converter, the portability of the E-bike user can be maximized by excluding an external adapter. The validity of the proposed circuit will be confirmed by operation mode analysis and simulation. Moreover, experimental results of integrative charger using Li-ion battery and 200 W motor test will be showed with a prototype sample as well.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.12 s.354
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• pp.83-88
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• 2006

In this paper, we propose a new cross bar embedded structure for improvement of attenuation characteristics along the different lossy media. A general characterization procedure based on the extraction of the characteristic impedance and propagation constant for analyzing a single MIS(Metal-Insulator-Semiconductor) transmission line used and an analysis for a new substrate shielding MIS structure consisting of grounded crossbars at the interface between Si and Sio2 layer using the Finite-Difference Time-Domain(FDTD) technique is used. In order to reduce the substrate effects on the transmission line characteristics, a shielding structure consisting of grounded cross bar lines over time-domain signal has been examined. The extracted, distributed frequency-dependent transmission line parameters as well as the line voltages and currents, and also corresponding equivalent circuit parameters have been examined as function of frequency. It is shown that the quality factor of the transmission line can be improved without significant changes in the characteristic impedance and effective dielectric constant.

• Korean Journal of Materials Research
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• v.29 no.3
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• pp.196-203
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• 2019

We report on the fabrication and characterization of an oxide photoanode with a zinc oxide (ZnO) nanorod array embedded in cuprous oxide ($Cu_2O$) thin film, namely a $ZnO/Cu_2O$ oxide p-n heterostructure photoanode, for enhanced efficiency of visible light driven photoelectrochemical (PEC) water splitting. A vertically oriented n-type ZnO nanorod array is first prepared on an indium-tin-oxide-coated glass substrate via a seed-mediated hydrothermal synthesis method and then a p-type $Cu_2O$ thin film is directly electrodeposited onto the vertically oriented ZnO nanorod array to form an oxide p-n heterostructure. The introduction of $Cu_2O$ layer produces a noticeable enhancement in the visible light absorption. From the observed PEC current density versus voltage (J-V) behavior under visible light illumination, the photoconversion efficiency of this $ZnO/Cu_2O$ p-n heterostructure photoanode is found to reach 0.39 %, which is seven times that of a pristine ZnO nanorod photoanode. In particular, a significant PEC performance is observed even at an applied bias of 0 V vs $Hg/Hg_2Cl_2$, which makes the device self-powered. The observed improvement in the PEC performance is attributed to some synergistic effect of the p-n bilayer heterostructure on the formation of a built-in potential including the light absorption and separation processes of photoinduced charge carriers, which provides a new avenue for preparing efficient photoanodes for PEC water splitting.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.4
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• pp.85-98
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• 2003

Computational power of IC chip is improved day after day producing IC chips holding co-processor continuously. Also a lot of wireless terminals which IC chip embedded in are produced in order to provide simple and various services in the wireless terminal market. However it is difficult to apply the key distribution protocol under wired communication environment to wireless communication environment. Because the computational power of co-processor embedded in IC chip under wireless communication environment is less than that under wired communication environment. In this paper, we propose the hey distribution protocol appropriate for wireless communication environment which diminishes the computational burden of server and client by using co-processor that performs cryptographic operations and makes up for the restrictive computational power of terminal. And our proposal is satisfied with the security requirements that are not provided in existing key distribution protocol.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.11
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• pp.1377-1383
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• 2019

Histogram equalization is the most frequently used algorithm for image enhancement. Its hardware implementation significantly outperforms in time its software version. The overall performance of FPGA-based implementation of histogram equalization can be improved by applying pipelining in the design and by exploiting the multipliers and a lot of SRAM blocks which are embedded in recent FPGAs. This work proposes how to implement a fast histogram equalization circuit for 8-bit gray level images. The proposed design contains a FIFO to perform equalization on an image while the histogram for next image is being calculated. Because of some overlap in time for histogram equalization, embedded multipliers and pipelined design, the proposed design can perform histogram equalization on a pixel nearly at a clock. And its dual parallel version outperforms in time almost two times over the original one.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.2
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• pp.175-181
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• 2024

In electrical power substations, bulky iron-core potential transformers (PTs) are installed in a tank of gas-insulated switchgear (GIS) to measure system voltages. This paper proposed a low-power voltage transformer (LPVT) that can replace the conventional iron-core PTs in response to the demand for the digitalization of substations. The prototype LPVT consists of a capacitive voltage divider (CVD) which is embedded in a spacer and an impedance matching circuit using passive components. The CVD was fabricated with a flexible PCB to acquire enough insulation performance and withstand vibration and shock during operation. The performance of the LPVT was evaluated at 80%, 100%, and 120% of the rated voltage (38.1 kV) according to IEC 61869-11. An accuracy correction algorithm based on LabVIEW was applied to correct the voltage ratio and phase error. The corrected voltage ratio and phase error were +0.134% and +0.079 min., respectively, which satisfies the accuracy CL 0.2. In addition, the voltage ratio of LPVT was analyzed in ranges of -40~+40℃, and a temperature correction coefficient was applied to maintain the accuracy CL 0.2. By applying the LPVT proposed in this paper to the same rating GIS, it can be reduced the length per GIS bay by 11%, and the amount of SF6 by 5~7%.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1066-1070
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• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.131-131
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• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility ($\sim900cm^2/Vs$). These electronic properties allow high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances, the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. This paper studies different channel dimensons ($L_{CH}$ : $0.5{\mu}m$, $1\;{\mu}m$, $1.5\;{\mu}m$) and their effect on the the device transient characteristics. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship. with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. We observe an increase in the turn-on and turn-off time with increasing the channel length. The switching time in 4H-SiC DMOSFETs have been found to be seriously affected by the various intrinsic parasitic components, such as gate-source capacitance and channel resistance. The intrinsic parasitic components relate to the delay time required for the carrier transit from source to drain. Therefore, improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance.