• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.2
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• pp.56-63
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• 2011

This paper presents the method of giving hysteresis characteristics to the digital input port of microprocessors or micro-controllers and it's design procedures. And this paper shows the example of circuit design and the effect of this method by experiments. Presented method has advantages : By the additional one port and two resistors, input port can have hysteresis characteristics and hysteresis band is larger than TTL, CMOS schmitt trigger gates.

• Journal of Sensor Science and Technology
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• v.29 no.1
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• pp.51-58
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• 2020

In this study, a novel method for sweeping automatic linearization of wavelength swept laser is proposed. Through the test performed on the implemented laser, the linear sweeping is held up well with a 97% decrease in nonlinearity, and 60 nm sweeping range, 1 kHz sweeping frequency, and 8.8 mW average optical power were obtained. The proposed method uses fiber Bragg grating array, optical-electronic conversion circuit, FPGA embedded module, and a LabVIEW program to generate new compensated wave patterns which were applied to the fiber Fabry-Perot tunable filter. Linear sweeping can reduce the cumbersome and time-consuming recalibration process required for nonlinear sweeping. Additionally, the proposed method provides more accurate measurement results for the structure safety monitoring system.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.27-30
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• 2003

The recent technology developments introduce new difficulties into the test process by the increased complexity of the chip. Most widely used method for testing high complexity and embedded systems is built-in self-test(BIST). In this paper, we describe 5-stage pipeline system as circuit under testing(CUT) and proposed a BIST scheme for the hazard detection unit of the pipeline system. The proposed BIST scheme can generate sequential instruction sets by pseudo-random pattern generator that can detect all hazard issues and compare the expected hazard signals with those of the pipelined system. Although BIST schemes require additional area in the system, it proves to provide a low-cost test solution and significantly reduce the test time.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.817-824
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• 2016

A simultaneous bidirectional transceiver over a single wire has been developed in a 65 nm CMOS technology for a command and control bus. The echo signals of the simultaneous bidirectional link are cancelled by controlling the decision level of receiver comparators without power-hungry operational amplifier (op-amp) based circuits. With the clock information embedded in the rising edges of the signals sent from the source side to the sink side, the data is recovered by an open-loop digital circuit with 20 times blind oversampling. The data rate of the simultaneous bidirectional transceiver in each direction is 75 Mbps and therefore the overall signaling bandwidth is 150 Mbps. The measured energy efficiency of the transceiver is 56.7 pJ/b and the bit-error-rate (BER) is less than $10^{-12}$ with $2^7-1$ pseudo-random binary sequence (PRBS) pattern for both signaling directions.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.244-245
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• 2005

This paper presents the performance of BALUN embedded in the LTCC substrate of ZigBee system which is one of the kind of wireless communication. The BALUN is used to make two signal which have 180$^{\circ}$ phase difference and 3dB power from one input signal. Therefore, this is 3-port network circuit. At the center frequency(915MHz), insertion losses were 3.1dB and 3.4dB, respectively. Also, the phase difference was 182$^{\circ}$. Its size is 2.1$\times$3.6mm. The Used materials were dupont9599 LTCC ceramic and daejuo086 Ag.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.3
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• pp.13-17
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• 2002

In ceramic systems, many components including embedded passives and TRL(transmission line) are used for composition of 3-dimensional circuit. So the exact analysis on this components must be performed. As for the TRL's, material properties including electrical conductivity of metal, loss factor and effective dielectric constant of dielectric material and geometrical factors like roughness of surface, vias, dimension of stripline structure have a large effect on the charactersistics of transmission lines. In this research, effect of material and geometrical factors on the characteristics of stripline structure is analyzed and quantified by simulation and measurement.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.2
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• pp.83-88
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• 2015

Core-A is 32-bit synthesizable processor core with a unique instruction set architecture (ISA). In this paper, the Core-A ISA is introduced with discussion of useful features and the development environment, including the software tool chain and hardware on-chip debugger. Core-A is described using Verilog-HDL and can be customized for a given application and synthesized for an application-specific integrated circuit or field-programmable gate array target. Also, the GNU Compiler Collection has been ported to support Core-A, and various predesigned platforms are well equipped with the established design flow to speed up the hardware/software co-design for a Core-A-based system.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.249-250
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• 2008

In this paper, we propose the single polycrystalline silicon flash EEPROM IC with a new structure which does not need the high voltage switching circuit. The design of high voltage switching circuits which are needed for the data program and erase, has been an obstacle to develop the single-poly EEPROM. Therefore, we has proposed the new cell structure which uses the low voltage switching circuits and has designed the full chip. A new single-poly EEPROM cell is designed and the full chip including the control block, the analog block, row decoder block, and the datapath block is designed. And the each block is verified by using the computer simulation. In addition, the full chip layout is performed.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.165-168
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• 2002

Accurate circuit simulation models for embedded RF passive components in LTCC provide a way to efficiently design high performance RF modules. Particularly, consideration of unavoidable parasitic components is required certainly. In this study, the parasitic components which is appeared from 3-D structure is considered.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.1 no.2
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• pp.123-129
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• 2008

In this paper, we propose the algorithm and circuit implementation to improve the performance of Multiplication using Addition based on H421 code. We expect that our method will be an essential element to make a embedded prototype in Ubiquitous environment.